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A novel single chip clock distribution circuit is described that is a self-calibrating synchronization system that receives a periodic, digital clock signal as a reference and generates multiple system clock signals that dynamically track and are synchronized to the reference clock across temperature, voltage, and process variations. This chip is used as an integral part of the clock distribution for a fault tolerant computer system. FUNCTIONAL OVERVIEW OF THE CLOCK CHIPModem high speed digital systems require clock signals to be distributed to many loads throughout the system with as little skew as possible. Clock distribution can be realized with commercially available parts [ 11, however, this approach is usually limited for the following reasons -these parts are restricted to about IO outputs or less, the guaranteed minimum and maximum delay differences across parts is several nanoseconds, and the ground bounce noise for parts with 'ITL I/O can be as large as several volts [2]. The clock circuit described in this paper* overcomes the aforementioned limitations, and incorporates some additional features that are beneficial towards reducing system wide clock skew. It handles interrupted and un-interrupted power supply changes (IPS and UPS). Two groupings of outputs exist to drive CMOS (ASIC) and TTL (non-ASIC) loads. The chip is designed such that the delay between these two goupings can be varied from about 2ns to about 5ns in steps of about 45qPs with the ASIC to NONASIC delay line.A picture of the clock chip die without metal 3 is shown in Fig. 1. The usage of the gate array is quite small, much less than 50%. The clock circuit is composed of several functional blocks that are integrated on a single chip. These blocks are:Fine delay line, phase detector, multiplexers and deglitch circuits, control state machine, and ASIC to NONASIC delay line. The chip has three modes of operation: Test, search, and track.A state machine controls the operation of these modes, and allows the chip to track continuously during system operation. It also interfaces to an extemal diagnostic processor which monitors the operation and state of the clock chip. Further, the state machine initiates the search for the reference during *Patent Pending system power up, and manages the clock operation during power loss. The state machine also limits delay tracking variations from clock cycle to clock cycle so as not to introduce unacceptable clock jitter as seen at the loads.The chip contains special deglitch circuits which insure clean waveforms after changes in the select pins of the multiplexers. The phase detector is composed of 6 flip-flops and a delay line. The statistical metastability MTBF settling time of the 1st flipflop stage not resolving its output within 19ns is calculated to be over 4 million years. This assumes a unity gain bandwidth product of 2.5 Gradians, a clock frequency of 50 MHz, and a data frequency of 12.5 MHz [3]. The chip is packaged in a controlled impedance PGA. U 0 pin assignments are based on Time Domain Refl...