Abstract:A fully reconfigurable architecture of a LDPC (lowdensity parity check) decoder for IEEE 802.11n system is proposed in this paper. This architecture can be operated in 12 kinds of modes specified in IEEE 802.11 system. Under the proposed architecture, memory usage and hardware complexity obviously improved, as compared with the other research works. Furthermore, the proposed decoder also able to support multi-rate and multi-size LDPC codes decoding. The proposed decoder was implemented in UMC 0.18 μm CMOS technology. The maximum operating frequency is measured 200 MHz and the corresponding power dissipation is 691.23 mW and total area is 4.61 mm 2 . Keywords: IEEE 802.11n, LDPC decoder, layered belief propagation, early termination, reconfigurable Classification: Electron devices, circuits, and systems [1] IEEE 802.11n Wireless LAN Medium Access Control MAC and Physical Layer PHY specification, IEEE 802. 11n-D1. 0, 2006 [2] J. Chen and M. P. C. Fossorier, "Near optimum universal belief propagation based decoding of low-density parity-check codes," IEEE Trans. References