We present a CMOS-compatible optoelectronic directed logic architecture that achieves high computational throughput (number of operations per second per unit area) by its ultracompact form factor. High speed-to-power performance is also achieved, by the low capacitance and high junction-to-mode overlap of low-radii SOI vertical pn junction microdisk switches. By using wavelength-division multiplexing and two electrical control signals per disk, each switch performs (N)OR, (N)AND, and X(N)OR operations simultaneously. Connecting multiple switches together, we demonstrate higher-order scalability in five fundamental N-bit logic circuits: AND/OR gates, adders, comparators, encoders, and decoders. To the best of our knowledge, these circuits achieve the lowest footprint of silicon-based multigigabit-per-second optical logic devices in literature.

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The performance of integrated silicon photonic devices is sensitive to small structural variations that arise from imperfections in the nanofabrication process. This sensitivity is exacerbated for next-generation devices that require fine feature sizes to push the limits of performance. In this work, we present a deep convolutional neural network model to predict fabrication variations in planar silicon photonic devices and verify their manufacturing feasibility prior to prototyping. Our model is trained on a modest set of scanning electron microscope images of structures that experience dimensional inaccuracies stemming from combined contributions from proximity effects in lithography and loading effects in dry etching. Our model quickly and accurately predicts over/under-etching, corner rounding, filling of narrow channels and holes, and washing away of small features in a photonic device. With this, the expected performance of a device can be predicted through an extra simulation and any necessary design corrections can be made prior to fabrication.

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