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This paper presents a new method of designing digital signal processors for very large scale integrated (VLSI) circuit implementation with residue number systems (RNS), as opposed to the binary number systems traditionally used. In an RNS, a number is represented by its residues, modulo a set of relatively prime integers. The basic operations of modulo addition and multiplication are simpler in RNS because they can be executed independently in each residue class. Consequently, a desired linear function can be executed in a set of parallel channels on a chip, where each channel performs the same calculation modulo the integer used in that channel. Complexity is thus reduced by two mechanisms. Interconnections between parallel channels are eliminated and all operations are performed modulo the small integer used in each parallel channel of the RNS structure. The square law of circuit complexity applied to this set of small integers results in small, simple circuits. Speed of computation is increased because carry propagation delays are avoided. Further, the RNS design is combined with systolic arrays in such a way that the desired function becomes a parallel set of nearest neighbor-connected identical cells, each of which is minimally complex. The regularity minimizes interconnections and design time --only one master VLSI macrocell that can be optimized and replicated under computer-aided design (CAD) control is needed. In addition, two levels of redundancy can readily be incorporated to achieve concurrent test and fault tolerance: (1) redundant parallel residue channels can be used, and (2) error detection techniques can be efficiently incorporated into each of the systolic array cells that compose the parallel RNS channels. When the error detection indicates a persistent error in a given cell, the cell can be automatically replaced by a cell appended to the end of that particular RNS channel, thus effecting self-healing.The RNS/systolic method is illustrated by the design of a digital transversal filter which is projected for single chip implementation in 1.25 micron technology to have more than 5 x 10 2 gate Hz/cm2 throughput rate. A proof-of-concept filter has been implemented in 4 micron nMOS by 23 custom chips, each of approximately 20,000 transistor complexity. The filter has a combination of characteristics unachievable with other design techniques --128 fully programmable taps and 136 dB dynamic range, yet it contains only 150,000 gates and has 5 MHz throughput in 4 micron nMOS. Conventional radix-2 design techniques would require more than two million gates, would have less than 1 MHz throughput, and would project to 10 chips in 1.25 micron technology. In addition, the design method successfully reduced the work effort required for 20 of the 23 chips to the design of a single 225-gate master cell. APPROACHThree thresholds must be crossed for VLSI to have full impact.

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