A methodology for modeling the manufacturability of MOS transistors and circuits has been developed. The models are based on a small set of measurable process characterization parameters, whose variation explains the range of performance seen during production. A statistical MOSFET model, based on these measurable process parameters, was developed using global optimization and regression modeling of key fitting parameters to accurately predict transistor characteristics over a wide range of process variation. These same process parameters can be measured on the manufacturing floor, both in-line and at electrical test, and used to predict the performance of the fabricated integrated circuit before packaging and final test. The models for use in manufacturing and design are integrated, and data taken from the manufacturing line can be used to identify process shifts as well as to suggest design improvements for manufacturability enhancement. IntroductionIn today's competitive semiconductor manufacturing environment, it is important to be able to anticipate the effects of processing variation while still designing the product, and to characterize and control this variation while producing it [1,2]. In this work we present a methodology for modeling IC performance in terms of a simple set of process characterization data. First, a MOSFET model is developed, which utilizes a set of process parameters to predict transistor performance across the range of process variation seen on the fabrication line. At the design stage, the MOSFET model can be used for statistical circuit simulation in order to test the manufacturability of the design. These parameters can also be measured during production, and used to predict the performance of fabricated parts, early in the production cycle. A compact, product-specific performance prediction model is built from a combination of simulation results and manufacturing data. The prediction model can be used with production data for process control and production planning.This method has been applied on a commercial 1 Mbit EPROM fabricated in a 1.5 pm CMOS process.This work is based in previous physically based, statistical device modeling efforts [3,4,5]. Despite these previous efforts, however, Design for Manufacturability (DFM) still has limited use in the semiconductor industry. There are several reasons for this problem which are addressed in this research.First, early work in statistical modeling relied heavily on the use of process simulation, with the accompanying prohlem of tuning the simulator to match an actual manufacturing line [6]. The method presented in this work does not rely on process simulation, but uses data collected from transistor characterization, in conjunction with straightforward device physics. Further, the use of manufacturing data ensures that the parameters are measurable using production line capable techniques, and that they explain most of the variation seen on an actual fab line.Secondly, the early statistical device models were verified by matching a...

Competition in the semiconductor industry is forcing manufacturers to continuously improve the capability of their equipment. The analysis of real-time sensor data from semiconductor manufacturing equipment presents the opportunity to reduce the cost of ownership of the equipment. Previous work by the authors showed that time series filtering in combination with multivariate analysis techniques can be utilized to perform statistical process control, and thereby generate real-time alarms in the case of equipment malfunction. A more robust version of this fault detection algorithm is presented. The algorithm is implemented through RTSPC, a software utility which collects real-time sensor data from the equipment and generates realtime alarms. Examples of alarm generation using RTSPC on a plasma etcher are presented.

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A model for integrated circuit (IC) binning has been built using measurements collected on a high volume manufacturing line. This model uses electrical measurements collected before packaging in order to predict the high speed performance of manufactured parts before final test. The applications of the model include aiding the packaging decision, production planning and scheduling, process characterization and control and design for manufacturability. IntroductionAs integrated circuit dimensions shrink, circuit performance variation due to random fluctuations in the fabrication process becomes increasingly important [ 1,2,3]. This paper discusses a method for modeling the performance of fabricated integrated circuits in terms of measurable process parameters. These models are meant to cover the entire range of process variation. A commercial 1 Mbit CMOS EPROM is used as the test vehicle for this experiment.The intended application for the model is for binning manufactured parts. Commodity ICs, such as memories, microprocessors, EPLDs, etc., are performance tested and then priced accordingly. In-line measurements and electrical test results for a manufactured wafer can be used to predict circuit performance before final wafer test. This will allow binning early in the fabrication process.The ability to perform in-line binning is important in manufacturing planning, since it will make possible the expediting of higher performance wafers through the fabrication line.A second application of this model is for IC Design for Manufacturability [4,51. This can be accomplished by using this modeling technique to characterize the sensitivity of a new IC design to the variation of each critical process parameter.Previous related work has focused on reducing the amount of testing required by eliminating redundant measurements [6,7]. However, the issue of predicting performance early in the manufacturing cycle is not addressed. The work presented here uses measurements available before final test. The particular example discussed in this paper uses wafer level electrical test data, with the future goal of using in-line data for performance testing.The underlying thesis of this work is that measurable variation in process parameters causes the performance variation in fabricated ICs. Therefore, the contribution of this work is that the performance model is developed from measurements on a high-volume manufacturing line, and not process and device simulation results, as is typical in previous publications [ 1,2,3,6,7]. This ensures that the pertinent parameters are measurable with a small error, and that they explain the variation seen on an actual fab line.This paper is organized as follows. First, a general overview of the method will be given. Next, descriptions of fabrication line variation, then the experimental design used to develop the model will be discussed. The results will then be presented, followed by our conclusions and plans for future work.

The semiconductor manufacturing industry is demanding improved algorithms for the detection and isolation of equipment faults. The real-time statistical process control (RTSPC) algorithm analyzes real-time sensor and actuator data for the detection of such faults. The software was evaluated using SECS-II (Serial Equipment Communication Standard) data from several commercial plasma etchers. These data were used to build statistical models which were then applied to data recorded during subsequent wafer processing. RTSPC was able to detect several faults related to failure of rf matching networks. For one of the rf match failures, the RTSPC alarm preceded the component failure by several weeks. This alarm was correlated to a shift in the critical dimension of wafers processed in this etcher. The statistical data filters included within RTSPC are discussed, as well as the characterization of the real-time data. Emphasis is placed on whether uni-variate, multivariate, or time-varying statistics are required to detect the faults seen on the etchers, and additional algorithms which would enhance the fault detection capability.