Pipelined Recurrent Neural Network (PRNN) has been used with lot of success in many applications. In recent works, we have also proven that the PRNN exhibits good performances when used for interference cancellation and channel parameters estimation for the different multiple access schemes proposed as physical layer of the Fourth Generation (4G) networks: Wideband Code Division Multiple Access (WCDMA), Orthogonal Frequency Division Multiplexing (OFDM) and Multi Carrier CDMA (MC-CDMA). The use of a unique PRNN based module for the three multiple access techniques addresses a major challenge for the 4G mobile terminals: embedding many access techniques for reduced area and resources costs. In this paper, we investigate the feasibility of practical hardware implementation of the proposed structure, this paper aims at implementing the Pipelined Recurrent Neural Network structure by using the VHDL. VHDL is the name of the IEEE 1076 Hardware Description Language standard for very high-speed digital circuit design. The RTL/logic synthesis tool; Galileo has been used in order to generate the gate level of the proposed structure. The Xilinx Virtex II family is chosen as target technology.

No abstract