This paper presents a Power Management Unit (PMU) powered by a 1 mm 2 solar cell on the same substrate to rise up the harvested voltage above 1.1 V. The on-chip solar cell and the PMU are fabricated in standard 0.18 μm CMOS technology achieving a form factor of 1.575 mm 2. The PMU is able to start up from a harvested power of 2.38 nW without any external kick off or control signal. The PMU features a continuous and two-dimensional Maximum Power Point Tracking (MPPT) working in open-loop mode to handle a harvested power range from nW to μW, by modifying both the charge pump topology and the switching frequency. The MPPT is based on four voltage level detectors that define five working regions depending on the illumination and on a self-tuning reference current for a fine adjustment of the switching frequency. The chip also includes an auxiliary charge pump to generate the voltage level necessary for the control circuit, implemented as a Pelliconi charge pump of 8 stages with NMOS transistors in Pwell as diodes. A Dickson charge pump with transmission gates as switches and with variable gain and capacitance per stage is also designed as the main charge pump. Finally, two relaxation oscillators are implemented to drive both charge pumps. This paper is accompanied by a video file demonstrating the PMU operation by powering an off-chip NAND gate.

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On-chip energy harvesting by means of integrated photovoltaic cells in standard CMOS technology can be successfully used to recharge or power-up integrated circuits with the use of charge pumps for voltage boosting. In this paper, a tool to facilitate the design of such structures is proposed consisting of an accurate model of the joint dynamics of the micro-photovoltaic cell and a capacitive DC/DC converter in the slowswitching limit regime. The model takes into account both the top and bottom parasitic capacitances of the flying capacitors. We assume a classical model for the photodiode whose photogenerated current is extracted from device-level simulations. The joint model is verified by circuit-level simulations achieving high accuracy and computation time savings of up to 1700×. The joint model shows that the voltage generated by an integrated photovoltaic cell connected to a capacitive DC/DC converter is not constant even under constant illumination. This phenomenon can only be reproduced through the joint model and failing to take it into account results in an error in the estimation of the time needed by the DC/DC converter to reach a given output voltage. We also demonstrate that the maximum output voltage reached by a DC/DC converter in the slow-switching limit regime when a photovoltaic cell is used as energy transducer depends on the switching frequency. Finally, the applicability of the model is illustrated through the optimization of time response and charge efficiency for the Dickson, Fibonacci, and exponential topologies in the case of implantable devices.