Taguchi method has been applied to optimize the 0 . 1 8~1 ASIC MOSFETs. We have proposed the suitable condition of MOSFETs to achieve the target of Vt variance, which is determined from the target of the yield and Idsat, which is determined from the demand of customers. When performing TCAD simulation, we have compounded the noise factors to reduce the number of the simulations. Based on Taguchi method, we have successfully reduced the Vt variance about half from the original device (i.e. increase the yield) and increased Idsat to meet the target in the real product.