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A pixel cell has been designed which has been optimized for a data push architecture readout. It retains the features of precedin$ designs which allow time stamping, analog signal processing, XY address recording, ghost elimination and sparse data transmission. It eliminates a number of problems inherent in previous designs by use of sampled data techniques, destructive readout, and current mode output drivers. This document examines the motivation for this new pixel and covers the theory of operation of the various blocks. A discussion of the tradeoffs affecting speed, power, device size, and radiation stability is included as weil.

A description of hybrid PIN diode arrays and a readout architecture for their use as a vertex detector in the SSC environment is presented. Test results obtained with arrays having 256 x 256 pixels, each 30 /im square, are also presented. The development of a custom readout for the SSC will be discussed, which supports a mechanism for time stamping hit pixels, storing their xy coordinates, and storing the analog information within the pixel. The peripheral logic located on the array, permits the selection of those pixels containing interesting data and their coordinates to be selectively read out. This same logic also resolves ambiguous pixel ghost locations and controls the pixel neighbor read out necessary to achieve high spatial resolution. The thermal design of the vertex tracker and the proposed signal processing architecture will also be discussed.