The emergence of high-precision timing systems in High Energy Physics motivates new developments in the domain of clock generation and distribution. Particularly, when considering the challenges arising from adopting advanced deep-submicron CMOS technology nodes, all-digital PLL and clock and data recovery (CDR) architectures constitute a promising option for future high energy physics (HEP) experiments. Both LC oscillator and ring oscillator-based all-digital PLL/CDR blocks for front-end ASICs were studied, designed, manufactured and characterized. Their design, the hardening considerations, as well as the performance obtained with these circuits are presented in this article.