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Using physics-based predictive technology CAD simulations, we show the improvements possible in device performance via strain engineering in vertically-stacked horizontal gate-all-around nanosheet Field-Effect transistors (NSFETs), which may outperform conventional FinFETs beyond 7 nm technology node. Effects of mechanical strain on NSFET variability is reported for the first time. We present a novel simulation approach for the analyses of random dopant fluctuation (RDF) and metal grain granularity (MGG) dependent variability in nanosheet transistors. The study encompasses topography simulation, which realistically reproduces a reported experimental nanosheet transistor. Device simulations are based on sub-band Boltzmann transport with 2D Schrödinger equation in the nanosheet cross-section and 1D Boltzmann transport along the nanosheet channel. The effects of mechanical stress and geometry dependence of the electrical characteristics are also reported. Critical design issues are outlined.

Gate-all-around (GAA) cylindrical Si channel nanowire field-effect transistor (NW-FET) devices have the potential to replace FinFETs in future technology nodes because of their better channel electrostatics control. In this work, 3D TCAD physics-based simulations are performed for the first time to evaluate the potential of NW-FETs at extreme scaling limits of 3 nm using quantum corrected 3D density gradient finite element simulations. Simulations are also performed to study the effects of process-induced variabilities, such as metal grain granularity (MGG) on 3 nm gate length device performance in the sub-threshold region. The importance of MGG induced variability for gate-all-around stacked devices having 3 horizontal nanowires in the 3 nm technology nodes is shown.

Applications of stress/strain are now part of technology 'boosters' in microelectronics industry among other technologies such as silicon-on-insulator or the metal gate/high-k techniques. Application of strain in channel significantly increases carrier mobility. Thus, there is a need to characterize the deformations at nanoscale in the semiconductor induced by the strain. Uniaxial compressive strain has been an indispensable performance booster for p-channel FinFETs. In this work, based on extensive 3D process and device simulations with mechanical stress simulations using finite element techniques, performance assessment of nanoscale trigate FinFETs with uniaxially strained-SiGe channel (fin) has been presented. A comprehensive study based on stress tuning parameters is carried out to investigate the possible highest amount of process induced stress transfer to SiGe fin for optimization of device performance. The impact of process-induced strain on carrier mobility enhancement in 7 nm technology node is another major focus of this study. The stress transfer efficiency is shown for different process conditions with different Ge content. Technology CAD simulations show that strain in the fin is larger for higher Ge contents in the SiGe layer for p-channel FinFETs. For the first time, conversion from biaxial compressive strain of SiGe to uniaxial compressive strain in SiGe layers via process simulation has been demonstrated and implemented in the virtual fabrication of uniaxially strained-SiGe channel (fin) tri-gate FinFETs. A detailed performance comparison has been performed with conventional bulk-Si tri-gate FinFETs.

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