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EXECUTNE SUMMARYThe step coverage capabilities of APCVD BSG films have been optimized and are presented on dimensionless diagrams. The results have been used for the design of a 1 pm DLM process and applied to the manufacturing of 16 K SRAMs as test vehicles. EXTENDED ABSTRACTThe Boron Silicon Glass films are deposited in a Watkins Johnson 998 atmospheric pressure CVD system. The best step coverage capabilities of BSG films have been obtained for a 4% boron concentration and an oxygen 1 hybride ratio of 7011.In these process conditions, various BSG film thicknesses (el) have been deposited on test structures composed of metal lines with different spacings (d), thicknesses (h), and sidewall profiles. The step coverage results are plotted on (el/h, h/d) dimensionless diagrams. The limit curve of void formation and abacus of equal lateral step coverage are shown for two metal profiles in Figure 1. The aspect ratio limit before void formation is 0.6 for metal lines with a re-entrant angle and 0.75 with a slopped sidewall profile.The planarization of the BSG films, realized by etchback with a SOG layer, has been studied in a RGV260 ALCATEL machine on test structures. With any BSG thicknesses or etchback quantities, a planarization with a total SOG sacrificial layer without void formation is possible only when the aspect ratio is lower than the previous limit (Figure 2).A BSG Interlevel Dielectric (ILD) has been determined for a 1 pm DLM process by using the previous dimensionless diagrams and considering the highest aspect ratios of the technology : 0.65 for stacked LOCOS, POLY and METAL 1 ; 0.75 inside a METAL 1 to SILICON contact. The BSG ILD process has been realized using a total SOG sacrificial layer and is shown in Figure 3 on these two structures. The good planarization of the ILD allows a very conformal METAL 2 step coverage (Figure 4).The electrical characterization has been performed on combs and serpentines of each conductive layer. The resistance ratios of serpentines on maximum topography in comparison with flat surface are around 1.2 for METAL 1 and 1.1 for METAL 2. These results confirm the good planarization capability of the BSG ILD. The leakage currents between layers or on the same level are always below 20 pA on these 1 mm2 comb serpentine structures, proving the good electrical properties of the BSG films.This DLM process has been used in a 1 pm CMOS twin tub technology and applied to the manufacturing of 16 K SRAMs as test vehicles. Life tests are under way and do not show any degradation of the DLM process with BSG dielectric. ACKNOWLEDGEMENTS