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There has been significant interest in transition metal dichalcogenides (TMDs), including MoS2, in recent years due to their potential application in novel electronic and optical devices. While synthesis methods have been developed for large-area films of MoS2, many of these techniques require synthesis temperatures of 800 °C or higher. As a result of the thermal budget, direct synthesis requiring high temperatures is incompatible with many integrated circuit processes as well as flexible substrates. This work explores several methods of plasma-assisted synthesis of MoS2 as a way to lower the synthesis temperature. The first approach used is conversion of a naturally oxidized molybdenum thin film to MoS2 using H2S plasma. Conversion is demonstrated at temperatures as low as 400 °C, and the conversion is enabled by hydrogen radicals which reduce the oxidized molybdenum films. The second method is a vapor phase reaction incorporating thermally evaporated MoO3 exposed to a direct H2S plasma, similar to chemical vapor deposition (CVD) synthesis of MoS2. Synthesis at 400 °C results in formation of super-stoichiometric MoS2 in a beam-interrupted growth process. A final growth method relies on a cyclical process in which a small amount of Mo is sputtered onto the substrate and is subsequently sulfurized in a H2S plasma. Similar results could be realized using an atomic layer deposition (ALD) process to deposit the Mo film. Compared to high temperature synthesis methods, the lower temperature samples are lower quality, potentially due to poor crystallinity or higher defect density in the films. Temperature-dependent conductivity measurements are consistent with hopping conduction in the plasma-assisted synthetic MoS2, suggesting a high degree of disorder in the low-temperature films. Optimization of the plasma-assisted synthesis process for slower growth rate and better stoichiometry is expected to lead to high quality films at low growth temperature.

PURPOSE PMOS transistor degradation due to Negative Bias Temperature Instability (NBTI) has been shown to be a major transistor reliability mechanism. The effect of PMOS NBTI on the minimum operating voltage of a cache cell (Vmin) has been recently demonstrated [I J, and the modeling of the degradation of ultra small gate area devices is vital for the accurate modeling of Vmin. Recent data and simulation has indicated that random fluctuations in device degradation are present under stress. This paper examines the source of these random fluctuations in device degradation due to PMOS NBTI.PMOS NBTI transistor degradation is an important reliability mechanism and has been shown to be one of the major limiters for product lifetime [2,3].PMOS N3TI effects originate from the formation of fixed oxide charge and the creation of interface states. These effects manifest themselves as shifts in threshold voltage and transconductance, For large gate area devices, these shifts can cause failure of digital circuits to meet timing windows or can create undesirable mismatch in analog circuits.Recent observations on PMOS devices with small gate areas show that the degradation of both drain current and threshold voltage appear to be subject to random fluctuations.These fluctuations increase a5 a function of stress time and are affected by the current density. It is believed that the additional instability is due a discrete random trapped charge effect, similar to what has been recently observed for discrete-trap memories [4]. The trapped charge can occur at random locations across the gate and can affect the drain current de-pending on the local current density. This paper examines the effects of PMOS NBTI-induced random fluctuations on device degradation. It clearly demonstrates that this geometric effect is due to the statistical nature of random trapped charge in the oxide and the effect of this charge on the percolation path through the channel of a small gate area device. MODELINGThe statistical nature of the random charge effect can be modeled in a similar fashion as has been done for random dopants. Charges placed at discrete points in the channel region can constrict the current flow in a small gate area devices by locally modifylng the threshold voltage. As illustrated in Figure 1, if random charges are placed at discrete points along a conducting path from source to drain, the current flow will be forced to areas of lower threshold voltage and could possibly be shut off entirely. CHANKEL FIGURE 1: ILLUSTRATION OF CURRENT FLOW FROM SOURCE TO DRAW IN A SMALL GATE AREA DEVICE. OPEN CIRCLE REPRESENT FILLED TRAPS THAT ALTER THE CURRENT FLOW FROM SOURCE TO DRAIN. Keyes [5] derived a relationship expressing the fluctuation in the threshold voltage as a function of channel doping and gate area. In this derivation, the probability of a conducting path from source to drain is determined by the local probability of a given area in the channel having a number of impurities less than a critical threshold, m,. This probability can be...

Abstracr -We describe a series of unique self-stressing, reliability test structures suitable for investigation of reliability failure mechanisms f&ot-camers, electromigration, oxide breakdown) under realistic integrated circuit operating conditions. These shuctures contain DC-controlled, high-frequency on-chip oscillators, which stress test shuctures. As a result, high-frequency (>200 MHz) stresstesting can be performed using less expensive DC test systems. In particular, we performed hot-camer stress-testing at frequencies up to 230 MHz, which is the highest stress frequency reported for inverters. For the 1 pm technology examined, the quasi-static model accurately describes the degradation. We also present the statistical variation in high-frequency, hot-camer-induced degradation for the first time and show variations with temperature to be consistent with DC stress results. Since only DC test systems are needed, these structures provide a simple method to calibrate reliability simulators and characterize high-frequency reliability effects.

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