The functionality of modern IC's increasingly suffers from substrate noise. Digital transistors switching at high frequencies are known to induce substrate noise through their bulk contacts. In addition, interconnect carrying aggressive, high-frequency signals is known to induce substrate noise through its capacitive coupling with the substrate. In this paper, we describe how our layout-to-circuit extractor SPACE builds a coherent interconnect/substrate model from a layout. The result is a comprehensive circuit model which can immediately be simulated by a regular circuit simulator. We evaluate our modeling approach by extracting a ring-oscillator layout and simulating the resulting circuit with HSPICE. We have done extractions under varying conditions; the simulation results give practical insight into relevant substrate noise phenomena.

For present-day micro-electronic designs, it is becoming ever more important to accurately model substrate coupling effects. Basically, either a Finite Element Method (FEM) or a Boundary Element Method (BEM) can be used. The FEM is the most versatile and flexible whereas the BEM is faster, but requires a stratified, layout-independent doping profile for the substrate. Thus, the BEM is unable to properly model any specific, layout-dependent doping patterns that are usually present in the top layers of the substrate, such as channel stop layers. This paper describes a way to incorporate these doping patterns into our substrate model by combining a BEM for the stratified doping profiles with a 2D FEM for the top-level, layout-dependent doping patterns, thereby achieving improved flexibility compared to BEM and improved speed compared to FEM. The method has been implemented in the SPACE layout to circuit extractor and it has been successfully verified with two other tools.

In mixed-signal designs, substrate noise originating from the digital part can seriously influence the functionality of the analog part. As such, accurately modeling the properties of the substrate as a noise-propagator is becoming ever more important. A model can be obtained through the Finite Element Method (FEM) or the Boundary Element Method (BEM). The FEM performs a full 3D discretization of the substrate, which makes this method very accurate and flexible but also slow. The BEM only discretizes the contact areas on the boundary of the substrate, which makes it less flexible, but significantly faster. A combination between BEM and FEM can be efficient when we need flexibility and speed at the same time. This paper briefly describes the BEM and the FEM and their combination, but mainly concentrates on the theoretical validation of the combined method and the experimental verification through implementation in the SPACE layout to circuit extractor and comparison with commercial BEM and FEM tools.

Abstract. In present-day IC's, substrate noise can have a significant impact on performance. Thus, modeling the noise-propagation characteristics of the substrate is becoming ever more important. Two ways of obtaining such a model are the Finite Element Method (FEM) and the Boundary Element Method (BEM). The FEM makes a full 3D discretization of the entire substrate and is very accurate and flexible, but, in general, it is also slow. The BEM only discretizes contact areas on the substrate-boundary, and is usually faster, but less flexible, because it assumes the substrate to consist of uniform layers. Sometimes, layout-dependent doping patterns near the top of the substrate may also play a significant role in noise-propagation. The FEM would easily be able to model such patterns, but it can often be too slow. The BEM, on the other hand, might not always be accurate enough. This paper describes a combination between BEM and FEM, which results in a method that is faster than FEM but more accurate than BEM. Through a number of experiments, the method is validated and successfully verified against 2 commercially available tools.