Three-dimensional (3D) silicon integration of active devices with through-silicon vias (TSVs), thinned silicon, and silicon-to-silicon fine-pitch interconnections offers many product benefits. Advantages of these emerging 3D silicon integration technologies can include the following: power efficiency, performance enhancements, significant product miniaturization, cost reduction, and modular design for improved time to market. IBM research activities are aimed at providing design rules, structures, and processes that make 3D technology manufacturable for chips used in actual products on the basis of data from test-vehicle (i.e., prototype) design, fabrication, and characterization demonstrations. Three-dimensional integration can be applied to a wide range of interconnection densities (,10/cm 2 to 10 8 /cm 2 ), requiring new architectures for product optimization and multiple options for fabrication. Demonstration test structures, which are designed, fabricated, and characterized, are used to generate experimental data, establish models and design guidelines, and help define processes for future product consideration. This paper 1) reviews technology integration from a historical perspective, 2) describes industry-wide progress in 3D technology with examples of TSV and silicon-silicon interconnection advancement over the last 10 years, 3) highlights 3D technology from IBM, including demonstration test vehicles used to develop ground rules, collect data, and evaluate reliability, and 4) provides examples of 3D emerging industry product applications that could create marketable systems.

System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and highperformance integration of heterogeneous chip technologies and to support robust chip manufacturing with high-yield/low-cost chips for a wide range of two-and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. Highdensity wiring and high-density chip I/O interconnection can enable tight integration of heterogeneous chip technologies which approximate the performance of an integrated system-on-chip with a ''virtual chip'' using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density chip microbump interconnections scale to smaller size. In addition to heterogeneous chip integration, SOP products may leverage the integration of passive components, active devices, and electrooptic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications.

An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed. IntroductionThe last few decades have seen an astonishing increase in the functionality of computational systems. This capability has been driven by the scaling of semiconductor devices, which has enabled the number of transistors on a single chip to grow at a geometric rate, following Moore's Law [1]. In particular, the scaling of silicon metal-oxide semiconductor field-effect transistors (MOSFETs) [2] drives the effort to continue this trend into the future.However, several serious roadblocks exist. The first is the difficulty and expense of continued lithographic scaling, which could make it economically impractical to scale devices beyond a certain pitch. The second is that even if lithographic scaling can continue, the power dissipated by the transistors will bring clock frequency scaling to a halt. In fact, it could be argued that clock frequency scaling has already stopped, and microprocessor designs have increasingly relied on new architectures to improve performance. These factors suggest that in the near future, it will no longer be possible to improve system performance through scaling alone, and that additional methods to achieve the desired enhancement will be needed. Three-dimensional (3D) integration technology offers the promise of being a new way of increasing system performance, even in the absence of scaling. This promise is due to a number of characteristic features of 3D integration, including decreased total wiring length (and thus reduced interconnect delay times), a dramatically increased number of interconnects between chips, and the ability to allow dissimilar materials, process technologies, and functions to be integrated. Motivation for 3D integration

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