3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections

Sakuma, Katsuyuki; Andry, Paul; Tsang, C. K.; Wright, S. L.; Dang, Bing; Patel, C.S.; Webb, Bucknell C.; Maria, Joana; Sprogis, E.; Kang, Sung K.; Polastre, R.; Horton, R.; Knickerbocker, John

doi:10.1147/jrd.2008.5388567

Cited by 151 publications

(55 citation statements)

References 35 publications

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“…A critical structural element in the 3-D interconnects is the through-silicon via (TSV), which directly connects stacked structures die-to-die. Use of TSVs in 3-D integration can effectively improve system performance and reduce manufacturing costs [5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Stress-Induced Delamination Of Through Silicon Via Structures

Ryu¹,

Lu²,

Im³

et al. 2011

AIP Conference Proceedings

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Articles you may be interested inMicro-Raman spectroscopy and analysis of near-surface stresses in silicon around through-silicon vias for threedimensional interconnects J. Appl. Phys. 111, 063513 (2012); 10.1063/1.3696980Micro-scale measurement and modeling of stress in silicon surrounding a tungsten-filled through-silicon via J. Appl. Phys. 110, 073517 (2011) Abstract. Continuous scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32 nm technology node in microelectronics. Recently threedimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Thermo-mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper examines the effect of thermal stresses on interfacial reliability of TSV structures. First, the three-dimensional distribution of the thermal stress near the TSV and the wafer surface is analyzed. Using a linear superposition method, a semi-analytic solution is developed for a simplified structure consisting of a single TSV embedded in a silicon (Si) wafer. The solution is verified for relatively thick wafers by comparing to numerical results obtained by finite element analysis (FEA). Results from the stress analysis suggest interfacial delamination as a potential failure mechanism for the TSV structure. Analytical solutions for various TSV designs are then obtained for the steady-state energy release rate as an upper bound for the interfacial fracture driving force, while the effect of crack length is evaluated numerically by FEA. Based on these results, the effects of TSV designs and via material properties on the interfacial reliability are elucidated. Finally, potential failure mechanisms for TSV pop-up due to interfacial fracture are discussed.

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Section: Introductionmentioning

confidence: 99%

Stress-Induced Delamination Of Through Silicon Via Structures

Ryu¹,

Lu²,

Im³

et al. 2011

AIP Conference Proceedings

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“…[1][2][3][4][5] Also, 3D integration technology makes it possible to stack heterogeneous systems. [4][5][6] A wire-bonding method has been widely used to interconnect stacked chips. This method has several disadvantages such as long connection length, deterioration of high frequency characteristics, and limited connection between chips.…”

Section: Introductionmentioning

confidence: 99%

“…This method has several disadvantages such as long connection length, deterioration of high frequency characteristics, and limited connection between chips. 4,[7][8][9] To overcome these wiring connection problems, 3D chip stacking technology using a through Si via (TSV) has received increased attention. For vertical interconnection between chips, Cu to Cu bonding with a thin solder capping layer has been adapted for 3D chip stacking.…”

Section: Introductionmentioning

confidence: 99%

Chip to Chip Bonding Using Cu Bumps Capped with Thin Sn Layers and the Effect of Microstructure on the Shear Strength of Joints

Kim

Woo

Kim

2014

Journal of Elec Materi

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Chip to chip bonding techniques using Cu bumps capped with thin solder layers have been frequently applied to 3D chip stacking technology. We studied the effect of joint microstructure on shear strength. Joints were formed by joining Sn/Cu bumps on a Si die and Sn/Cu layers on another Si die at 245-330°C using a thermo-compression bonder. Three different types of microstructures were fabricated in the joints by controlling the bonding temperature and time, (1) a Sn-rich phase with a Cu 6 Sn 5 phase at the Cu interfaces, (2) a Cu 6 Sn 5 phase in the interior with a Cu 3 Sn phase at the Cu interfaces, and (3) one single Cu 3 Sn phase throughout the whole joint. The joint having a single Cu 3 Sn phase had the highest shear strength. Specimens were aged up to 2000 h at 150°C and 180°C. During aging, the microstructures of all joints were transformed in a single Cu 3 Sn phase. The shear strength of the joints was very sensitive to the formation of Cu 3 Sn and microvoids. Microvoids formed in the solder joints with a Cu 6 Sn 5 phase with and without a Sn-rich phase during aging and decreased the shear strength of the joints. Conversely, aging did not induce the formation of microvoids in the joints which originally had only a Cu 3 Sn phase and the shear strength was not decreased.

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“…1). Use of TSVs in 3-D integration can effectively improve system performance and reduce manufacturing costs [5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Thermomechanical Reliability Challenges For 3D Interconnects With Through-Silicon Vias

Ryu

Zhang

et al. 2010

AIP Conference Proceedings

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3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections

Cited by 151 publications

References 35 publications

Stress-Induced Delamination Of Through Silicon Via Structures

Stress-Induced Delamination Of Through Silicon Via Structures

Chip to Chip Bonding Using Cu Bumps Capped with Thin Sn Layers and the Effect of Microstructure on the Shear Strength of Joints

Thermomechanical Reliability Challenges For 3D Interconnects With Through-Silicon Vias

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