Stress-Induced Delamination Of Through Silicon Via Structures

Abstract

Articles you may be interested inMicro-Raman spectroscopy and analysis of near-surface stresses in silicon around through-silicon vias for threedimensional interconnects J. Appl. Phys. 111, 063513 (2012); 10.1063/1.3696980Micro-scale measurement and modeling of stress in silicon surrounding a tungsten-filled through-silicon via J. Appl. Phys. 110, 073517 (2011) Abstract. Continuous scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32 nm technology node in microelectronics. Recently threedimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Thermo-mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper examines the effect of thermal stresses on interfacial reliability of TSV structures. First, the three-dimensional distribution of the thermal stress near the TSV and the wafer surface is analyzed. Using a linear superposition method, a semi-analytic solution is developed for a simplified structure consisting of a single TSV embedded in a silicon (Si) wafer. The solution is verified for relatively thick wafers by comparing to numerical results obtained by finite element analysis (FEA). Results from the stress analysis suggest interfacial delamination as a potential failure mechanism for the TSV structure. Analytical solutions for various TSV designs are then obtained for the steady-state energy release rate as an upper bound for the interfacial fracture driving force, while the effect of crack length is evaluated numerically by FEA. Based on these results, the effects of TSV designs and via material properties on the interfacial reliability are elucidated. Finally, potential failure mechanisms for TSV pop-up due to interfacial fracture are discussed.

Thermomechanical characterization and modeling for TSV structures

“…9a). A previous study has suggested that via extrusion could be caused by interfacial delamination [19]. However, in the present study, no evidence of interfacial delamination was observed.…”

Intermetallic compounds in 3D integrated circuits technology: a brief review

“…Sukharev [ 43 ] and Lau [ 44 ] reported finite element analysis simulations of TSV upon electromigration (EM) failure, which is when the TSV is unable to deliver the necessary voltage to any circuitry gate. Ryu et al [ 45 ] and Stiebing et al [ 46 ] suggested considering thermal cycling, which causes the TSV to extrude from the surrounding matrix or substrate. This phenomenon occurs due to a coefficient of thermal expansion mismatch between the surrounding substrate and the metal filler in TSV.…”

Predicting Package Level Failure Modes in Multi Layered Packages

“…The vias have structures that go through the entire substrate and the stresses can be higher in the middle of the stack than the flanges. The stress field induced by differential thermal expansion in the via is threedimensional in nature [1]. It is necessary to investigate the stresses in the stacked via to get the full picture.…”