further SCF-LMO and experimental studies on such systems as B3C2H6, B7C2H9, B8C2Hio, Bi0Hh, and the isomers of Bi0C2Hi2. Such investigations are now in progress.Acknowledgments. We thank J. H. Hall, Jr., for helpful discussion and the Office of Naval Research for financial support. D. S. M. and I. R. E. are grateful to the National Science Foundation for predoctoral fellowships. Portions of this study were supported by a grant from the Research Corporation to I. R. E.

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We have assembled an integrated view of the entire via manufacturing process. This integrated study includes five key plasma processes that culminate in the production of vias on CMOS wafers. There are essentially no linear cross-correlations between the processing steps and there are no linear correlations between the individual process steps and the yield for vias, as measured by the resistance between metal-one (M1) and metaltwo (M2).Using a neural network, we demonstrate that the key processing steps to determine the M1M2 resistance are the thick oxide deposition and the anisotropic via etch. Of lesser significance are the etchback planarization, an isotropic etch and plasma enhanced tetra-ethoxy siliane (PETEOS) deposition. Keeping in mind that there are five processing steps, the numerical value of M1M2 resistance can be predicted ahead of time, before completion of all five processes. This prediction can be done to an accuracy of about 1 : By using adaptive neural networks, the intelligent agents can modify their predictive behavior with respect to process changes effected by the engineering staff. Our pre-production demonstration suggests that these programs could be used in feedback and feedforward control for production yield.

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