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In this paper we describe changes in a subject of digital logic design to fit the new plan of Bologna. The subject has a significant increase in hours of laboratory and students compared to previous years. We present the results of a student satisfaction survey and a comparison of the success of overcoming the remaining subject compared to past years.

The main objective of this paper is to develop a distributed architecture for integrating micro-electromechanical system (MEMS or microsystem) based on a hierarchical communications system governed by a master node. A MEM integrates a sensor with its signal conditioner and communications interface, thus reducing mass, volume and power consumption. In pursuing this objective, we developed an interface to connect MEMS on a sensor or microinstrument network. Interface model was developed using VHSIC hardware description language (VHDL). The implemented model or intellectual property (IP) core can be easily added to the microsystem or MEM. The core thus developed contains an interface file system (IFS) that supplies all the information related to the micro-system that we wish to connect to the network, allowing the specific characteristics to be isolated to the micro-instrument. The IFS allows all the nodes to have the same interface from the network point of view. In order to support complexity management and composability of the microinstrument, the IFS has a real-time service interface and a configuration interface. A functional characteristic of this configuration interface is the automatic new node integration or plug and play on network. The design was implemented in a field programmable gate array (FPGA) and was successfully tested. The FPGA implementation makes the designed nodes small-size, flexible, customizable, reconfigurable or reprogrammable with advantages of well-customized, costeffective, integration, accessibility and expandability. The VHDL hardware solution is a key feature for size reduction. The system can be resized according to its needs taking advantages of the VHDL configurability.