A highly-integrated optical phase-locked loop with a phase/frequency detector and a single-sideband mixer (SSBM) has been proposed and demonstrated for the first time. A photonic integrated circuit (PIC) has been designed, fabricated and tested, together with an electronic IC (EIC). The PIC integrates a widely-tunable sampled-grating distributed-Bragg-reflector laser, an optical 90 degree hybrid and four high-speed photodetectors on the InGaAsP/InP platform. The EIC adds a single-sideband mixer, and a digital phase/frequency detector, to provide single-sideband heterodyne locking from -9 GHz to 7.5 GHz. The loop bandwith is 400 MHz.

A highly integrated 40 Gbit/s coherent optical receiver is reported using a Costas loop as a homodyne optical phase locked loop (OPLL). A photonic IC, an electrical IC, and a hybrid loop filter are characterized, and the feedback loop system is fully analyzed to build a stable homodyne OPLL. All components are integrated on a single substrate within the compact size of 10 × 10mm(2), and a 1.1 GHz loop bandwidth and a 120 psloop delay are achieved. The binary phase-shift keying receiver exhibits error-free (BER<10(-12)) up to 35 Gbit/s and BER<10(-7) for 40 Gbit/s with no latency, and consumes less than 3 W power.

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T he topic of impedance transformation and matching is one of the well-established and essential aspects of microwave engineering. A few decades ago, when discrete radio-frequency (RF) design was dominant, impedance matching was mainly performed using transmission-lines techniques that were practical due to the relatively large design size. As microwave design became possible using integrated on-chip components, area constraints made L C section matching (using lumped passive elements) more practical than transmission line matching. Both techniques are conveniently visualized and accomplished using the well-known graphical tool, the Smith chart.Since CMOS technology was primarily and initially developed for digital purposes, the lack of high-quality passive components made it practically useless for RF design. The device speed was also far inferior to established III-V technologies such as GaAs heterojunction bipolar transistors (HBTs) and high-electron mobility transistors (HEMTs). The first RF CMOS receiver was constructed at 1989 [1], but it would take another several years for a fully integrated CMOS RF receiver to be presented. The scaling trend of CMOS in the past two decades improved the transistors' speed exponentially, which provided more gain at RF frequencies and also enabled operation at millimeter-wave (mm-wave) frequencies. The

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