This work proposes a refactoring for VeriSc testbenches in order to reduce the efforts that are required during the integration phase. This refactoring improves the reuse of testbench components that were developed during the verification of stand-alone blocks and preserves the other desirable features of VeriSC, such as tool support for the testbench construction, reuse of testbench components during the decomposition phase, synthesis of new coverage criteria during the composition phase.