The next generation Opteron ™ processor integrates 4 enhancedperformance x86 cores, each with 512kB L2 cache and an enhanced 128-bit FPU. The cores are integrated with a shared 2MB L3 cache and an enhanced on-chip memory controller that supports up to 4 16-bit HyperTransport ™ links and a dual-channel 128-bit DDR2/DDR3 interface. The design contains nearly 450M transistors and is fabricated in a 65nm SOI CMOS process with dual stress liners and embedded SiGe for PMOS source/drains. The design uses 11 layers of copper interconnect (Fig. 5.4.1) that include advanced low-k dielectrics. In a 95W max power envelope, the target frequency is 2.2 to 2.8GHz at 1.15V. The SoC chip is designed to facilitate maximum reuse of functional components and to provide the flexibility to create targeted variations.The processor is based on a flexible clocking architecture designed to easily scale across die configurations. Each core contains its own PLL, clock distribution system, and power grid, which can be independently power/performance managed by varying the frequency and voltage. The core voltage and the individual core frequencies are independent of the on-chip Northbridge, allowing them to enter power-efficient states while the processor interface runs at full speed to service DDR memory and HyperTransport ™ traffic. The clock distribution system is designed for a worst case systematic skew of 12ps in each core.To provide clocking flexibility and reduce communication latency between the processor and the northbridge, an asynchronous FIFO buffer absorbs the global clock skews and clock rate variations. The FIFO enables a modular design style when building die with a large number of cores and is fundamental to minimizing the core-to-Northbridge latency. A synchronous mode is provided in the FIFO buffer for tester determinism. To provide reverse compatibility with previous AMD Opteron ™ processors, this chip incorporates only one differential clock receiver to receive the 200MHz clock reference. The reference clock is distributed across the die to each core PLL, Northbridge PLL, HyperTransport ™ link, and DDR memory interface. The reference clock network contains special power-supply-filtered buffers to reduce the clock jitter created by a large clock-tree network. For thermal control, each of the 4 cores contains 8 remote temperature sensors scattered across the core and connected to a thermal evaluation (TCEN) circuit. The Northbridge contains 6 additional remote sensors connected to a fifth TCEN circuit. The 5 TCEN circuits are connected to a global thermal control (TCON) circuit that instructs the remote controllers to collect thermal measurements and report the results. The remote sensor contains a diode array and additional control circuits. The temperature is determined by measuring voltage drops while forcing a range of currents. The TCEN block contains differential switched-capacitor integrators that perform the arithmetic operations and convert the analog temperature into a 9-bit digital value. A first-order ∆Σ conve...

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