Although the number of total knee replacement (TKR) surgeries is growing rapidly, functionality and pain-reduction outcomes remain unsatisfactory for many patients. Continual monitoring of knee loads after surgery offers the potential to improve surgical procedures and implant designs. The goal of this study is to characterize a triboelectric energy harvester under body loads and to design compatible frontend electronics to digitize the load data. The harvester prototype would be placed between the tibial component and polyethylene bearing of a TKR implant. The harvester generates power from the compressive load. To examine the harvester output and the feasibility of powering a digitization circuitry, a triboelectric energy harvester prototype is fabricated and tested. An axial tibiofemoral load profile from normal walking (gait) is approximated as a 1 Hz sine wave signal and is applied to the harvester. Because the root mean square of voltages generated via this phenomenon is proportional to the applied load, the device can be simultaneously employed for energy harvesting and load sensing. With an approximated knee cyclic load of 2.3 kN at 1 Hz, the harvester generated output voltage of 18 V RMS, and an average power of 6 μW at the optimal resistance of 58MΩ. The harvested signal is rectified through a negative voltage converter rectifier and regulated through a linear-dropout regulator with a combined efficiency of 71%. The output of the regulator is used to charge a supercapacitor. The energy stored in the supercapacitor is used for low resolution sensing of the load through a peak detector and analog-to-digital converter. According to our analysis, sensing the load several times a day is feasible by relying only on harvested power. The results found from this work demonstrate that triboelectric energy harvesting is a promising technique for self-powering load sensors inside knee implants.

A methodology is proposed to exploit the interdependence between setup-and hold-time constraints in static timing analysis (STA). The methodology consists of two phases. The first phase includes the interdependent characterization of sequential cells, resulting in multiple constraint pairs. The second phase includes an efficient algorithm that exploits these multiple pairs in STA. The methodology improves accuracy by removing optimism and reducing unnecessary pessimism. Furthermore, the tradeoff between setup and hold times is exploited to significantly reduce timing violations in STA. These benefits are validated using industrial circuits and tools, exhibiting up to 53% reduction in the number of constraint violations as well as up to 48% reduction in the worst negative slack, which corresponds to a 15% decrease in the clock period.

In this article, the self-supported power conditioning circuits are studied for a footstep energy harvester, which consists of a monolithic multilayer piezoelectric stack with a force amplification frame to extract electricity from human walking locomotion. Based on the synchronized switch harvesting on inductance (SSHI) technology, the power conditioning circuits are designed to optimize the power flow from the piezoelectric stack to the energy storage device under real-time human walking excitation instead of a simple sine waveform input, as reported in most literatures. The unique properties of human walking locomotion and multilayer piezoelectric stack both impose complications for circuit design. Three common interface circuits, for example, standard energy harvesting circuit, series-SSHI, and parallel-SSHI, are compared in terms of their output power to find the best candidate for the real-time-footstep energy harvester. Experimental results show that the use of parallel-SSHI circuit interface produces 74% more power than the standard energy harvesting counterpart, while the use of series-SSHI circuit demonstrates a similar performance in comparison to the standard energy harvesting interface. The reasons for such a huge efficiency improvement using the parallel-SSHI interface are detailed in this article.

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Electrical Engineering Stony Brook University 2012Three primary techniques for manufacturing through silicon vias (TSVs), viafirst, via-middle, and via-last, have been analyzed and compared to distribute power in a three-dimensional (3-D) processor-memory system with nine planes. Due to distinct fabrication techniques, these TSV technologies require significantly different design constraints, as investigated in this work. A valid design space that satisfies the peak power supply noise while minimizing area overhead is identified for each technology. It is demonstrated that the area overhead of a power distribution network with via-first TSVs is approximately 9% as compared to less than 2% in via-middle and via-last technologies. Despite this drawback, a via-first based power network is typically overdamped and the issue of resonance is alleviated. A via-last based power network, however, exhibits a relatively low damping factor and the peak noise is highly sensitive to number of TSVs and decoupling capacitance.iii To my dearest parents, Jayashree Krishnamurthy and Satheesh Lakshminarayana.