Deep neural network (DNN) inference task offloading is an essential problem of edge intelligence, which faces the challenges of limited computing resources shortage of edge devices and the dynamics of edge networks. In this article, the DNN inference task offloading problem in queue‐based multi‐device and multi‐server collaborative edge computing is investigated. To support efficient collaborative inference, we formulate a multi‐objective optimization problem that minimizes the average delay and maximizes average inference accuracy. Due to time‐varying queue load states and random task arrival, it is challenging to solve this optimization problem. Thus, a deep reinforcement learning based task offloading algorithm, named LSTM‐TD3, is proposed to solve the formulated problem. Specifically, LSTM‐TD3 incorporates the long short‐term memory (LSTM) and twin delayed deep deterministic policy gradient algorithm (TD3), and can leverage long‐term environment information to efficiently explore the optimal task offloading solution. Finally, we compared the performance of LSTM‐TD3 with TD3 (without LSTM) and random offloading algorithms, and simulation results show the LSTM‐TD3 reduce the average inference delay by up to 21.6%, and the accuracy is better than other algorithms.
RISC-V is an open-source and royalty-free instruction set architecture (ISA), which opens up a new era of processor innovation. RISC-V has the characteristics of modularization and extensibility, and explicitly supports domain-specific custom extensions. Nowadays, RISC-V is a popular ISA for embedded processors. However, there is still a gap between the capabilities of RISC-V and the requirements of various emerging computing scenarios (e.g., artificial intelligence, cloud computing). Recently, the RISC-V standards organization has continuously introduced new ISA extensions to meet the needs of advanced computing. There are also a variety of novel research proposed customized extensions of RISC-V for certain scenarios. As far as we know, there is a lack of a survey to systematically present the research progress of RISC-V ISA extensions. The goal of this paper is to provide a comprehensive survey on existing works about RISC-V ISA extensions. First, the application scenarios of RISC-V are introduced, and the requirements for ISA extensions are analyzed. Then, we survey the progress of official RISC-V ISA extension specification and recent research on RISC-V ISA extension. Finally, we highlight some possible future research opportunities on the RISC-V ISA extension.INDEX TERMS RISC-V, instruction set architecture, extensions, survey.
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