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An efficient architecture of two-dimensional (2D) Finite Impulse Response (FIR) filters is required to process the images. The architectures implemented in VLSI design and optimization achieve better performance in terms of metrics such as power consumption, area, and delay. The 2D FIR filter architectures can be implemented using parallel or block processing to increase the throughput of the architecture and to prune the number of clock cycles required for image processing. The symmetry in the filter coefficients decreases the number of multipliers, whereas the multiplier block is very complex and a power hunger block in the filter architecture. In this work, two types of symmetry architectures such as diagonal symmetry and quadrantal symmetry filters are proposed. The remaining multipliers required for the filter architecture are replaced by Distribute Arithmetic (DA) logic. The memory-based DA reduces the LUT size and hence the area, power, and delay are reduced in the filter architecture. Block processing, symmetry, and DA concepts are introduced here to optimize the 2D FIR filter architecture. The proposed architectures are implemented in 45nm CMOS technology using Cadence Genus Synthesis tools and area, delay, power, Area-Delay Product (ADP), and Power-Dealy Product (PDP) results are obtained and compared with state-of-the-art works. The ADP value of the proposed diagonal symmetry architecture is decreased by a maximum of 73.35%, and a minimum of 28.9%, and the PDP value is decreased by a maximum of 87%, and a minimum of 21.27% when compared to the existing works. The ADP and PDP values of the proposed quadrantal symmetry are decreased by a minimum of 28.9%, and 27.74% when compared to the works, respectively.

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Field Programmable Gate Arrays (FPGAs) are significant in digital designs, Scientific Computing, Digital Signal Processing and Telecommunications. To use re-configurable technology in the portable applications, the devices that consume significantly less power and programmable are essential. In FPGAs, leakage power has become a major component as the technology evolves to deep sub-micron. An effective way to reduce leakage power is to parallelly employ both Power Gating and MTCMOS techniques in the designs. The elementary impression is design of Re-Configurable Look-Up Tables (LUT) in which logic gates are controlled by sleep transistors to reduce the leakage power. For turning off logic gates, the input of the sleep transistor is controlled by a control signal. A 4-bit Arithmetic Logic Unit (ALU) is designed with these LUTs and found that power dissipation is reduced by 40%. The control signal is given in such a way that the non-used blocks of the design are completely turned off by using Power gating technique and the leakage power is reduced by using MTCMOS technique. LUTs are designed in CADENCE Virtuoso Schematic Editor and simulated for verification in Analog Design Environment.