A high-resolution phase frequency detector (PFD) is designed for highfrequency signal detection and low jitter phase locked loop applications. The proposed PFD eliminates the reset path delay and usage of any latches, minimise the dead zone to near zero by generating narrow pulses at each input rising edge. In addition, the designed PFD completely removes unwanted output glitches, accepts inputs with a large difference in frequency, and also has the ability to drive a large capacitive load with minimal impact on performance. The proposed PFD is designed in 90 nm CMOS technology with a 1.2 V power supply. Simulation results indicate that the proposed design can operate over a wide range of frequencies from 10 kHz to 6 GHz and can detect phase differences for inputs as small as 125 fs for all frequencies of operation and for all process corners. The simulated power consumption is 75 µW at 166.6 MHz with an input phase difference of 125 fs.Introduction: Phase frequency detectors (PFDs) are widely used in micro-electronic circuit designs including phase locked loops (PLLs), radars, and interferometers. A PFD is a key sub-circuit to the operation of a PLL. The purpose of a PFD is to compare two periodic input signals and generate output pulses indicative of the phase and frequency difference of the two periodic input signals [1]. Conventional PFDs are designed by using D flip-flops with a reset path as feedback loop. This conventional PFD has the drawbacks of high power consumption, large dead zone, limited operating speed, and undesired output glitches [2]. Improved design topologies manage to reduce dead-zone errors [3] to 15 ps and attempt to simplify design circuitry. Pass transistor-based logic PFD [4] designs try to minimise the number of transistors to improve performance benchmarks, but such designs are subjected to output voltage drops and performance is affected greatly by adding output load capacitance. An alternative flip-flop-based design [5] has been proposed to reduce the dead-zone error to near 750 fs, but it has a drawback of large power consumption and moderate operating frequency due to its circuit complexity and long critical path. The dead zone is defined as the minimum bound of phase error where PFD is unable to detect the difference in input phase. Therefore, the dead zone plays an important role in the operation of a PFD since dead-zone errors introduce jitter to PLL devices [6].In this Letter, a new design topology without any feedback path is presented to improve dead zone of the PFD while simplifying the design to reduce power consumption. The proposed PFD design accepts two input phase differences over the complete range [0, 2π]. The output glitches are completely removed and this PFD can drive large capacitive loads without affecting its normal operation. Dead-zone error of the PFD design is reduced to almost zero by removing the reset path.

This paper presents a high-frequency wide tuning range Digital Control Oscillator (DCO) with In-phase and Quadrature outputs designed using a 90nm CMOS process with 1.2 V power supply. The proposed design operates in the frequency range of 1.1-8.2GHz. The designed ring oscillator with digital control inputs attains high oscillation frequencies by applying negative delay inputs to the transistors in parallel to the conventional static CMOS inverter. The stage delay of the ring oscillator with the proposed design is less than the conventional static CMOS inverter and the skewed delay inverter cell. At 2.02GHz oscillation frequency, the measured phase noise is -90.43dBc/Hz at an offset of 1 MHz and -117.64dBc/Hz at an offset of 10MHz. Keywords-Digital Control Oscillator (DCO), All-DigitalPhase Lock Loop (ADPLL), skewed delay, high frequency, wide tuning range, ring oscillator.I.