Abstract. An 8 bit segmented current steering DAC is presented for the compensation of mismatch of sensors with current output arranged in a large arrays. The DAC is implemented in a 1.8 V supply voltage 180 nm standard CMOS technology. Post layout simulations reveal that the design target concerning a sampling frequency of 2.6 MHz is exceeded, worst-case settling time equals 60.6 ns. The output current range is 0–10 μA, which translates into an LSB of 40 nA. Good linearity is achieved, INL < 0.5 LSB and DNL < 0.4 LSB, respectively. Static power consumption with the outputs operated at a voltage of 0.9 V is approximately 10 μW. Dynamic power, mainly consumed by switching activity of the digital circuit parts, amounts to 100 μW at 2.6 MHz operation frequency. Total area is 38.6 × 2933.0 μm2.

Abstract. The subject of this work is a low noise amplifier (LNA), operating in the frequency range 1.8-2.1GHz. The CMOS 0.13μm technology is used in respect to the low cost of the final device. Among the specifications, a variable gain and an adjustable working frequency are required. In particular, four different working modes are provided: 1.8, 1.9 and 2.1GHz high gain and 2.1GHz low gain. The amplifier is designed to be used as first stage of a receiver for mobile telephony. For this reason low power consumption is taken into consideration (low supply voltage and low drain currents). A simple digital circuit, integrated on-chip, is used to select the operating mode of the LNA by means of two input pins. A Noise figure of 1dB is obtained with a supply voltage of 0.8V.

Wideband Sigma-Delta A/D-converters must make use of low oversampling ratios, so that the sampling frequency remains acceptably low. In order to obtain high resolutions, the alternatives are increasing the bit-number of the internal quantizer or the loop-order. As high order single-loop modulators are prone to instability, cascaded structures are usually employed. To relax the mismatch sensitivity inherent to cascaded structures, we use a third rather than a second order modulator in the first loop. The proposed 3(5-bit)-2(2-bit) cascaded modulator achieves an effective resolution of 14-Bits over a bandwidth of 12.5MHz with an Oversampling ratio (OSR) of only 8 taking into account all non-idealities. The Signal-to-Quantization-Noise-Ratio (SQNR) is maximized, thanks to the optimized 5-th-order noise transfer function (NTF), which has two pairs of complex conjugate zeros and one dc-zero. Low distortion is achieved through feed-forward paths, which add the signal direct at the quantizer input, relaxing the integrator specifications.

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