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This paper presents a CMOS realization of a time-to-digital converter (TDC) for nuclear physics experiments. An innovative and robust architecture, already used in a previous TDC version with 1 ns of bin size, has been adopted and improved with the aim to achieve a 500-ps bin size. The TDC has eight input channels plus a common channel. It can store up to 32 events per channel with a double-hit resolution of 8 ns. It can realize common-start and common-stop operations. It has 4.2 ms of input range with a 125-MHz system clock, The chip uses an asynchronous interpolator system based on a delay-locked Line to increase the coarse resolution. It has been fabricated in a double-metal single poly n-well, 1-mu m CMOS process with an area of about 77 mm(2). Measurements show that the TDC has better performance compared to similar devices, especially the time resolution below 250 ps

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This paper presents a flexible Telemetry, Tracking & Command (TT&C) transponder for Earth Observation (EO) small satellites. The proposed device adds to the state-of-the-art EO TT&C transponders the possibility of scientific data transfer thanks to the high downlink data-rate (up to 40 Mbps) and in-flight reconfigurability via Telecomand (TC). The integration of these features in one single device represents a considerable optimization in terms of mass budget, which is important for EO small satellites. Furthermore, in-flight reconfigurability of communication parameters via TC is important for in-orbit link optimization, which is especially useful for Low-Earth Orbit (LEO) satellites where visibility can be as short as few hundreds of seconds. The proposed transponder is a digital radio unit working at 70 MHz intermediate frequency (IF). A new custom and configurable hardware accelerator was developed to cover intensive radio DSP functions at IF. The custom hardware is integrated in a single FPGA with a space-compliant processor core, for control, configuration and interface with the other satellite subsystems. All the quantization parameters were fine-tailored to reach a trade-off between hardware complexity and implementation loss (IL). The IF RX/TX ports require eight bits and seven bits, respectively. The IL is 0.5 dB at BER = 10-5 for the RX chain. A system proof-of-concept was implemented on the Xilinx Virtex 6 VLX75T-FF484 FPGA. The total device occupation is 82%. The power consumption of the design fitted in FPGA is less than 2 W. The power consumption of the whole demonstrator board is less than 9 W.

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