surge that happens during the power restore sequence does not Abstract-At the 90-nm, leakage currents bring standby power cause any issues. to an unacceptable level and circuit level techniques become The complexity of SoC level leakage management can be mandatory. However applying these techniques must be robust handled by a divide-and-conquer approach. The SoC is split and practical. In this paper we focus not only on leakage into several power managed IPs [2]. We defined an IP as PM reduction solutions but also on their deployment as a worldwide (Power Managed) if it can be put in retention or in off mode infrastructure as the added-value resides not only in the u techniques themselves but also in the way they are implemented usdin taed sing, We gating and D iod fote SaM to build an efficient, re-usable, robust, low cost and portable as drep on igur 1. We qualian iP a se bi prt ath platform. Techniques have been silicon proven on the 90-nm TI PM framework if it is compliant with a set of rules for CMOS technology and is commonly used to design SoC with regularity (homogenous metal grid, embedded power switches complexities over 100 Million transistors. on a regular pitch ... ) and present a standardized set of signals acting as a power control interface (similar to the 5 pins JTAG Index Terms--SoC Design, Leakage Power Management, standard interface). Once a complete library of PM IPs Wireless Application processor.