A wide variety of voltage mixers and samplers are implemented with similar circuits employing switches, resistors, and capacitors. Restrictions on duty cycle, bandwidth, or output frequency are commonly used to obtain an analytical expression for the response of these circuits. This paper derives unified expressions without these restrictions. To this end, the circuits are decomposed into a polyphase multipath combination of single-ended or differential switched-series-kernels. Linear periodically timevariant network theory is used to find the harmonic transfer functions of the kernels and the effect of polyphase multipath combining. From the resulting transfer functions, the conversion gain, output noise, and noise figure can be calculated for arbitrary duty cycle, bandwidth, and output frequency. Applied to a circuit, the equations provide a mathematical basis for a clear distinction between a "mixing" and a "sampling" operating region while also covering the design space "in between." Circuit simulations and a comparison with mixers published in literature are performed to support the analysis.

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Abstract-At low GHz frequencies, analog time-delay cells realized by LC delay lines or transmission lines are unpractical in CMOS, due to their large size. As an alternative, delays can be approximated by all-pass filters exploiting transconductors and capacitors (g m -C filters). This paper presents an easily cascadable compact g m -C all-pass filter cell for 1-2.5 GHz. Compared to previous g m -RC and g m -C filter cells, it achieves at least 5x larger frequency range for the same relative delay variation, while keeping gain variation within 1dB. This paper derives design equations for the transfer function and several non-idealities. Circuit techniques to improve phase linearity and reduce delay variation over frequency, are also proposed. A 160nm CMOS chip with maximum delay of 550psec is demonstrated with monotonous delay steps of 13 psec (41 steps) and an RMS delay variation error of less than 10psec over more than an octave in frequency (1 -2.5GHz). The delay per area is at least 50x more than for earlier chips. The allpass cells are used to realize a four element timed array receiver IC. Measurement results of the beam pattern demonstrate the wideband operation capability of the g m -RC time delay cell and timed array IC-architecture.

Spatial interference rejection in analog adaptive beamforming receivers can improve the distortion performance of the circuits following the beamforming network, but is susceptible to the nonlinearity of the beamforming network itself. This paper presents an analysis of intermodulation product cancellation in analog active phased array receivers and verifies the distortion improvement in a four-element adaptive beamforming receiver for low-power applications in the 1.0-2.5-GHz frequency band. In this architecture, a constant-Gm vector modulator is proposed that produces an accurate equidistance square constellation, leading to a sliced frontend design that is duplicated for each antenna element. By moving the transconductances to RF, a fourfold reduction in power is achieved, while simultaneously providing input impedance matching. The 65-nm implementation consumes between 6.5 and 9 mW per antenna element and shows a +1 to +20 dBm in-band and out-of-beam third-order intercept point due to intermodulation distortion reduction.