No abstract

In this paper a differential single-port switched-RC N-path filter with bandpass characteristic is proposed. The switching frequency defines the center frequency, while the RC-time defines the bandwidth. This allows for high-Q highly tunable filters which can for instance be useful for cognitive radio. Using a linear periodically timevariant (LPTV) model, exact expressions for the filter transfer function are derived. The behavior of the circuit including non-idealities such as maximum rejection, spectral aliasing, noise and effects due to mismatch in the paths is modeled and verified via measurements. A simple RLC equivalent circuit is provided modeling bandwidth, quality factor and insertion loss of the filter. A 4-path architecture is realized in 65nm CMOS. An off-chip transformer acts as a balun, improves filter-Q and realizes impedance matching. The differential architecture reduces clock-leakage and suppresses selectivity around even harmonics of the clock. The filter has a constant -3dB bandwidth of 35MHz and can be tuned from 100MHz up to 1GHz. Over the whole band IIP3 is better than 14dBm, P 1dB =2dBm and NF<5.5dB,while the power dissipation increases from 2mW to 16mW (only clocking power).

An inductorless low-noise amplifier (LNA) with active balun is proposed for multi-standard radio applications between 100 MHz and 6 GHz. It exploits a combination of a common-gate (CG) stage and an admittance-scaled common-source (CS) stage with replica biasing to maximize balanced operation, while simultaneously canceling the noise and distortion of the CG-stage. In this way, a noise figure (NF) close to or below 3 dB can be achieved, while good linearity is possible when the CS-stage is carefully optimized. We show that a CS-stage with deep submicron transistors can have high IIP2, because the cross-term in a two-dimensional Taylor approximation of the () characteristic can cancel the traditionally dominant square-law term in the () relation at practical gain values. Using standard 65 nm transistors at 1.2 V supply voltage, we realize a balun-LNA with 15 dB gain, NF 3.5 dB and IIP2 +20 dBm, while simultaneously achieving an IIP3 0 dBm. The best performance of the balun is achieved between 300 MHz to 3.5 GHz with gain and phase errors below 0.3 dB and 2 degrees. The total power consumption is 21 mW, while the active area is only 0.01 mm 2 .

A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative "iterative" harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS.Measurements show 34 dB gain, 4 dB NF, and +3 5 dBm in-band IIP3 while the out-of-band IIP3 is +16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order 60 dB over 40 chips, while the digital AIC technique achieves 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply.Index Terms-Adaptive interference cancellation, adaptive signal processing, baseband processing, blocker, blocker filtering, CMOS, cross-correlation, digitally assisted, digitally enhanced, harmonic mixing, harmonic rejection, interference mitigation, linearity, LMS, low-noise amplifier (LNA), low-noise transconductance amplifier (LNTA), mismatch, multiphase, multiphase clock, nonlinearity, out-of-band interference, passive mixer, polyphase, receiver, robust receiver, SAW-less, software radio (SWR), software-defined radio (SDR), switching mixer, wideband receiver. A. Out-of-Band NonlinearityNonlinearity may generate intermodulation and harmonic distortion falling on top of the desired signal, or may desensitize a receiver due to blockers and produce cross modulation [10]. Without sufficient RF band-selection filtering, the out-of-band linearity can become the bottleneck since OBI is much stronger than IBI. A wideband LNA as used in [1] and [2] amplifies the desired signal and undesired wideband interference with equal 0018-9200/$26.00

This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115 225 m 2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 W and achieves an energy efficiency of 4.4 fJ/conversion-step.