A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$W at 1 MS/s

Elzakker, M. van; Tuijl, Ed van; Geraedts, P.F.J.; Schinkel, D.; Klumperink, Eric A.M.; Nauta, Bram

doi:10.1109/jssc.2010.2043893

Cited by 373 publications

(209 citation statements)

References 17 publications

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“…3(a) depicts the proposed dynamic comparator, modified from the one in [11]. The double-tail latch-type voltage comparator [12] allows the speed and offset to be optimized independently which makes the design more flexible. However, the cross-coupled inverters require quite a large voltage headroom to accomodate 2jV th j þ 2V ov to work in saturation which limits the achievable speed of the comparator at low supply voltage.…”

Section: Dynamic Comparator With Background Offset Calibrationmentioning

confidence: 99%

“…In the proposed method, two cross-coupled pair stages in parrallel called cross-coupled latches are adopted which aid faster decision based on stronge positive feedback path but with smaller headroom limitation (jV th j þ 2V ov ). In [12], only after the common-mode voltage exceeds the threshold voltage of input pair of the second stage, the voltage amplification in the second stage takes over. Differently, the transconductance stage consisiting of M1-M2 translates the first stage signal to latched stage at the begining of the comparision in proposed method which accelerates the decision speed.…”

Section: Dynamic Comparator With Background Offset Calibrationmentioning

confidence: 99%

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A 6 mW 325 MS/s 8 bit SAR ADC with background offset calibration

Zhu

Zhou

et al. 2017

IEICE Electron. Express

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An 8-b single-channel successive approximation register (SAR) analog-to-digital converter (ADC) fabricated in 55 nm CMOS is proposed. With segmented prequantize and bypass digital-to-analog converter (DAC), the unnecessary switching of high weight capacitors are avoided. Two alternating comparators are utilized to reset the comparators completely without the sacrifice of conversion speed. A novel simple and low power background offset calibration technique is implemented. Operating at 325 MS/s, this ADC consumes 6 mW from 1.2 V supply, achieves SNDR of 43.6 dB and SFDR of 59.1 dB with 11-MHz input while occupying 0.011 mm 2 .

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Section: Dynamic Comparator With Background Offset Calibrationmentioning

confidence: 99%

Section: Dynamic Comparator With Background Offset Calibrationmentioning

confidence: 99%

A 6 mW 325 MS/s 8 bit SAR ADC with background offset calibration

Zhu

Zhou

et al. 2017

IEICE Electron. Express

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“…The PUF array is composed of 128 identical PUF bit-cells that can provide 128-bit readouts at the clock rate of 1 MHz. Each PUF bit-cell is designed based on a dynamic two-stage comparator [4] and optimized to generate unique and reliable digital response. This bit-cell circuit consumes only transient current, which is proportional to the clock rate.…”

Section: S Tao and E Dubrovamentioning

confidence: 99%

Ultra‐energy‐efficient temperature‐stable physical unclonable function in 65 nm CMOS

Tao¹,

Dubrova²

2016

Electron. lett.

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An Ultra-Energy-Efficient Temperature-Stable Physical Unclonable Function in 65nm CMOS. Electronics LettersAccess to the published version may require subscription. N.B. When citing this work, cite the original published paper. Permanent link to this version:http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-183776An Ultra-Energy-Efficient Temperature-Stable Physical Unclonable Function in 65nm CMOS S. Tao and E. Dubrova Physical unclonable functions (PUFs) are promising hardware security primitives suitable for resource-constrained devices requiring lightweight cryptographic methods. This letter proposes an ultra-lowpower and reliable PUF based on a customized dynamic two-stage comparator operating in the sub-threshold region. The proposed PUF is implemented in a standard 65nm CMOS technology and validated through Monte-Carlo simulations. Evaluation results show a worst-case reliability of 98.3% over the commercial temperature range of 0• C to 85• C and 10% fluctuations in supply voltage. In addition, the 128-bit PUF array consumes only 1.33 µW at 1 Mb/s, which corresponds to 10.3 fJ/bit, being the most energy-efficient design to date.Introduction: Physical unclonable functions (PUFs) make use of the inherent process variation in physical devices to generate unique chip IDs or secure keys. For reliable identification/authentication, PUFs should be robust against varying operating environment conditions. Moreover, silicon PUFs are usually integrated into radio-frequency identification (RFID) tags and smart card ICs [1], which are powered by battery or even harvested energy. Therefore, the circuit implementation of these PUFs must be highly energy-efficient.Silicon PUFs developed up to now, either delay based (e.g., ring oscillator-and arbiter-PUFs) or memory based (e.g., SRAM-PUFs), mostly employ standard logic cells for circuit implementation. These conventional PUF designs have no flexibility to size the transistors for power/performance optimisation. In addition, they are generally very sensitive to environmental variations resulting in significantly increased errors in response bits. To improve the reliability, a few customized PUF implementations have been reported [2,3], which rely on analogue/static circuit blocks. In this work, we take a step further by proposing a PUF design that does not only show sufficient uniqueness and reliability, but also achieves excellent energy-efficiency.

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“…Unfortunately, such a procedure is extremely time-consuming and requires heavy data post-processing to estimate the static nonlinearity metrics as well as the Signal-to-Noise and Distortion Ratio (SNDR) and the Equivalent Number of Bits (ENoB). Similar issues arise also in many ultra-low-power designs where sub-10fF unit capacitors are adopted [16,10,11]. In this case, the impact of the DAC parasitics on the converter power consumption becomes not negligible and in a traditional EDA tool environment its estimate always relies on transient analyses, thus being time-consuming.…”

Section: Introductionmentioning

confidence: 95%

“…In terms of efficiency, for moderate speeds and resolutions that are typically required by the most of the aforementioned applications, charge redistribution successive approximation register (CR-SAR) converters are the best choice and dominate the ADC market. In the last decades, starting from the Classic Binary Weighted (CBW) SAR ADC [14], other solutions have been proposed to improve the efficiency [16,10] and adopted in various systems [12,9].…”

Section: Introductionmentioning

confidence: 99%

An efficient tool for the assisted design of SAR ADCs capacitive DACs

et al. 2016

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a b s t r a c tThe optimal design of SAR ADCs requires the accurate estimate of nonlinearity and parasitic capacitance effects in the feedback charge redistribution DAC. Since both contributions depend on the specific array topology, complex calculations, custom modeling and heavy simulations in common circuit design environments are often required. This paper presents a MATLAB-based numerical environment to assist the design of the charge redistribution DACs adopted in SAR ADCs. The tool performs both parametric and statistical simulations taking into account capacitive mismatch and parasitic capacitances computing both differential and integral nonlinearity (DNL, INL). An excellent agreement is obtained with the results of circuit simulators (e.g. Cadence Spectre) featuring up to 10 4 shorter simulation time, allowing statistical simulations that would be otherwise impracticable. The switching energy and SNDR degradation due to static nonlinear effects are also estimated. Simulations and measurements on three designed and two fabricated prototypes confirm that the proposed tool can be used as a valid instrument to assist the design of a charge redistribution SAR ADC and to predict its static and dynamic metrics.

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A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$W at 1 MS/s

Cited by 373 publications

References 17 publications

A 6 mW 325 MS/s 8 bit SAR ADC with background offset calibration

A 6 mW 325 MS/s 8 bit SAR ADC with background offset calibration

Ultra‐energy‐efficient temperature‐stable physical unclonable function in 65 nm CMOS

An efficient tool for the assisted design of SAR ADCs capacitive DACs

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