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This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115 225 m 2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 W and achieves an energy efficiency of 4.4 fJ/conversion-step.

Future systems powered by energy scavenging, e.g., wireless sensor nodes, demand μW-range ADCs with no static bias currents in order to have a power dissipation proportional to the sample rate. An ADC that meets these requirements by using a charge-redistribution DAC, a dynamic 2-stage comparator, and a delay-line-based controller is realized in CMOS. Figure 12.4.1 shows a DAC based on charge redistribution, with a binary-weighted capacitor array [1]. The left side of every capacitor can be switched between a low reference voltage, V ref-, and a high reference voltage, V ref+ , using a simple digital inverter. If the left side of capacitor C MSB is switched from low to high, the step on output V DAC is ΔV DAC = (V ref+ -V ref-)*C MSB /C tot , where C tot is the total capacitance at the output node. The effect of the charge-redistribution is reversible: if the left side of C MSB is switched from high to low, the output returns to its original value. This does not contribute any noise to the output voltage as there is no sampling involved. The switch at the output of the DAC can be used to reset the DAC voltage to V ref-to prevent DC drift due to leakage. This reset gives a thermal-noise voltage of kT/C tot .The matching of metal-plate capacitors in a modern CMOS process is very good. For a 10b converter with a total DAC capacitance C tot =600fF; the matching is better than 0.5 LSB. For this DAC, mismatch is dominant over thermal noise if the output-voltage range is more than ~0.2V. The inverter charging or discharging C MSB of 300fF only sees the equivalent capacitor C eq of 150fF. If V ref+ -V ref-is 1V it takes only 150 fJ to switch C eq from V ref-to V ref+ and back to V ref-. Thus, the theoretical energy per conversion in the DAC can be less than a few hundred fJ. This energy can even be lower if the charging and discharging of C eq is done in multiple steps. This is shown in Fig. 12.4.2 where the voltage over C eq is charged from 0 to V in 3 steps of V/3. The dissipated energy is 1/6C eq V 2 . which is 3× less than the ½C eq V 2 of a one-step charge. In theory, charging with n equidistant voltage steps always decreases the power by a factor of n. In practice control overhead is added and there is only a net saving for "small" values of n with "large" values of C eq . Switches are implemented as small NMOS or PMOS devices driven by logic. The intermediate voltage levels come from big capacitors C BIG1 and C BIG2 and automatically converge to appropriate values due to repetitive DAC operation. This implementation is allowed, because the accuracy of the intermediate steps does not affect the accuracy of the DAC. Only intermediate levels are used for the 3 MSBs, while the supply voltage is used directly for all other reference voltages.The charge-redistribution DAC can be used in a simple way to make a SAR ADC, as shown in Fig. 12.4.3. First, the DAC is reset to a state where the MSB is high and all other bits are low. Next, V in is sampled onto output V DAC . In a single-ended ADC, V DAC is compared to V half . ...

Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6 offset reliability at 5 Gb/s. Index Terms-Capacitive pre-emphasis transmitter, globally asynchronous, locally synchronous (GALS), interconnect, low-power design, low-swing, network on chip (NoC), on-chip communication, source synchronous, wave-pipelining. I. INTRODUCTION O N-CHIP communication has become an active research area in the past few years. This not only because on-chip interconnects are becoming a speed, power, and reliability bottleneck [1], but also because systems on chips (SoCs) start to become so complex that they require new interconnection approaches [2], [3]. Networks on chips (NoCs) have emerged as the seemingly best candidate to connect the many functional elements on present and future SoCs [2]-[7]. Most of the long (global) interconnects, which have the severest bandwidth limitations and crosstalk problems, are eliminated in a NoC, especially when mesh-like network configurations are used. An NoC also enables easier clock-distribution with alleviated skew requirements and less power consumption as the various processing elements can operate mesochronous [4]-[6] or asynchronous

Abstract-Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. Repeaters can partly bridge this gap, but the classical repeater insertion approach requires a large number of repeaters while the intrinsic data capacity of each interconnect-segment is only partially used. In this paper we analyze interconnects and show how a combination of layout, termination and equalization techniques can significantly increase the data rate for a given length of uninterrupted interconnect. To validate these techniques, a bus-transceiver test chip in a 0.13-m, 1.2-V, 6-M copper CMOS process has been designed. The chip uses 10-mm-long differential interconnects with wire widths and spacing of only 0.4 m. Differential interconnects are insensitive to common-mode disturbances (e.g., non-neighbor crosstalk) and enable the use of twists to mitigate neighbor-to-neighbor crosstalk. With transceivers operating in conventional mode, the chip achieves only 0.55 Gb/s/ch. The achievable data rate increases to 3 Gb/s/ch (consuming 2 pJ/bit) with a pulse-width pre-emphasis technique, used in combination with resistive termination.