There are many arithmetic operations which are performed, on a computer arithmetic unit, through the use of multipliers (e.g., exponential and trigonometric functions). Consequently, optimized multipliers are on demand while designing an arithmetic unit. On the other hand, given the advent of quantum computer and reversible logic, design and implementation of digital circuits in this logic has gained popularity. In reversible circuit design, decreasing three parameters is of interest: quantum cost, depth of the circuit and the number of garbage outputs. In this paper, we propose a novel reversible multiplier with the aim of decreasing the depth of the circuit while neither scarifying any extra quantum cost nor garbage outputs. The partial products, as is the case for prior works, are generated in parallel using Peres gates and thereafter a reversible multioperand adder consisting of reversible full-adders and halfadders produces the final product.

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Reversible circuits, nowadays, have found grounds * Depth: The number of l1x or 2x2 reversible gates in many applications such as low power CMOS design and which are in the longest path from input to output. quantum computing. In reversible circuit design, decreasing Reduction of these three parameters simultaneously is three parameters is of interest: quantum cost, depth of the circuit difficult. Therefore, one or two of them are usually opted as and the number of garbage outputs. On the other hand, recently, .' . t t decimal computer arithmetic, for the sake of its preciseness, gains the main parameter for minimization and try to reduce others popularity. Given that the BCD digit adder is the basic unit in as much as possible. In this paper a new method for designing decimal arithmetic, in this paper we propose a new reversible reversible circuits, with the aim of minimizing the depth of the design for this unit with the aim of minimizing the depth of the circuit is proposed and applied to the reversible one digit circuit. Furthermore, we show that the proposed designing BCD adder. Since depth in reversible circuits can be method can be applied to any other reversible circuit for considered as the latency in classic circuits, the proposed reaching the minimum depth.adder is based on Carry-Look-Ahead (CLA) topology which has been proved to be the fastest [5]. The rest of paper is organized as follows: reversible gates Power dissipation is one of the important considerations in are explained in section 2; the prerequisites of BCD adders digital circuit design. A part of this energy loss is due to are discussed in section 3 while in section 4 the proposed switches and materials. The other part arises from Landauer's design is presented; section 5 compares the new design with principle [1] where he proved that in irreversible circuits previous works and finally section 6 summarizes the outcome losing one bit of information dissipates KT.Ln2 joules of heat of this paper. energy, where K is the Boltzmann's constant and T is the absolute temperature. Although the amount of dissipating heat II. REVERSIBLE GATES for room temperature is small, it can not be neglected in someAn n x n reversible circuit consists of n inputs and n applications (e.g. quantum circuit design). Furthermore, outputs with mapping of each input assignment to a unique Bennett [2] showed that reversible circuits do not lose output assignent and vice versa. There are two main types of information due to the one-to-one mapping between inputs reversible gates: Toffoli [6] and Fredkin [7]. An n-bit Toffoli and outputs; hence no extra energy loss, gate passes the first (n-1) inputs to output unaltered (as controlIn the design of reversible circuits two restrictions should signals) and for the last output the nth input inverts (as target be considered: signal) if all previous (n-1) signals are '1'.