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As 3D integration matures and progress of the success of stacking and packaging is very thin and potentially ultra thin die from place them accurately into a target position packs, gelpaks or onto another wafer) damage to the die. The ability to do this is choice of tooling used to pick the die plus used to hold the wafer during dicing and su steps. Consideration must be given to how physically released from the tape and the size on the tooling used as part of the releaseThe interaction between three differen concepts and settings in combination with fo tapes based on two release mechanism; 1) U driven are studied. Focus is placed on ke namely the condition of the die post pick and chip outs) and the capability to pick a unpicked die on tape while taking the die si is found that the picking of even rel dimensions, such as 20x20mm 2 from bo possible with considerably high throughpu units per hour, when the right process para However, the die placement can cause issue die support. One solution is the usage o where the die is held flat and supported by general, the well known UV tape can succes die picking, where for some applications could be an attractive option.

Chip-to-wafer stacking is a key enabling technology for 2.5D as well as for 3D with technological challenges driven by on one hand the increase of the die surface and the number of I/Os and on the other hand by the reduction of the vertical dimensions. In our integration, the chips are reported on a silicon interposer containing copper via-middle TSVs. Two different approaches have been considered to realize chip-to-wafer stacking with respectively 35 and 20 μm ultra-thin dies. The first one is the conventional flip chip (or Face-to-Face, F2F) integration based on Cu/SAC μ-pillar connections while the second is a less classical Back-to-Face (B2F) way based on the realization of a high topology RDL after bonding the chips face up on the silicon interposer using a polymer. This last architecture becomes more and more attractive with the reduction of the chip thickness to ultra-thin dimension and can offer substantial advantages in terms of design flexibility and technology cost. Chip bonding is one of the first tasks to address: several bonding materials have been tested either on die side using die attach film (DAF) or on bottom interposer side using wafer level spin coated polymers. Then a novel brick consisting of high topology encapsulation and metallization has been fully developed to connect the dies to the bottom wafer enabled by the development of a specific lithography process. Thermo-mechanical FEM simulation and first reliability assessment have been carried out and support the good mechanical behavior of this integration. Electrical tests have been also completed that allows comparing the performances of F2F and B2F interconnections in terms of resistances and yield at front side level but also at back side level after TSV exposure. Back to Face integration can be very attractive in terms of process complexity and cost for ultra-thin chips with limited I/Os counts.

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