Nanoscale electronics is increasingly affected by disturbances caused by radiation, noise and effects of statistical process variations. Moreover, deliberate injection of faults into cryptographic circuits is used by malicious attackers to perform cryptanalysis and gain access to sensitive information. Error-detecting codes are employed to protect circuits against such disturbances, and new advanced codes specifically designed to counter malicious attacks have recently been introduced. However, a number of logic gates in the circuit are not adequately protected by the error-detecting code, as faults affecting these gates escape detection with a relatively high probability. We introduce a cross-level protection solution, where a light-weight error-detecting code is combined with hardening of insufficiently protected gates using transistor resizing. Such gates are determined by FPGA-supported fault injection. A thorough electrical analysis is performed in order to modify the electrical parameters of these gates such that faults are highly unlikely. We report area and power overhead for a number of error-detecting codes. To the best of our knowledge, this is the first work which co-optimizes fault handling by information redundancy based on error-detecting codes and by hardening individual circuit elements.

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