Fixed-width multipliers have two n-bits operands and produce an approximate n-bits results for their product. These multipliers discard part of the partial products matrix, to reduce hardware cost, and employ extra correction functions to reduce approximation error. While previous papers mainly focus on average error metrics (like mean-square error), we present an in-depth analysis of the maximum absolute error (MAE) of these circuits. The MAE is the main parameter to be considered in important applications, like function evaluation. We describe an efficient numerical method to compute the MAE in fixed-width multipliers and fixed-width multiplier-accumulator (MAC) circuits. Further we present a technique to compute a compensation function, that can be efficiently implemented in hardware, aimed to minimize the MAE. The novel fixed-width multiplier topologies proposed in the paper exhibit a MAE that is better than previously proposed solutions and that is close to the theoretical lower bound. As a practical application we employ the developed MAC with minimum MAE for the hardware computation of elementary functions, using piecewise linear approximation. Implementation results in a 65 nm technology and comparison with previously proposed architectures show that the topologies proposed in this paper allow reducing the MAE without worsening the electrical performances

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