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Abstract-Program execution can be accelerated with efficient use of cache in real-time systems. And each program has its own instruction access pattern, which causes uneven distribution of accesses to the sets of instruction cache. In multi-core real-time systems, mapping tasks with similar instruction access patterns to the same core will incur massive conflicts and degrade the utilization of the cache. This paper proposes a cache-aware cooperative task mapping method to improve system efficiency in multi-core real-time systems. Our method quantifies the access frequency of instruction cache sets for each task, and then select tasks with complementary distributions to run on the same core, which can reduce inter-task interference and shorten the cache refill delay during context switch. Evaluation results show that the utilization of the system is improved by about 8.92% with the method.

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Software architecture simulators are indispensable tools in modern processor design. According to the granularity of simulation, they can be classified into the fast functional simulation and the slow detailed one. The detailed simulator takes far longer time than the functional simulator when simulating the same workload. Based on the duration difference of them, we propose a Workload Segmented Parallel Simulation (WSPS) methodology to accelerate the detailed simulation by simulating different segments of the workload concurrently. The results on SPEC2Kint benchmarks show that, when programs are divided into 64 segments, the speedup is about 11.5, with the relative error of CPI and L1 cache hit-rate remaining lower than 1.5% and 0.01%, respectively. Also, the analysis indicates that WSPSbased simulation can achieve even much higher speedup when using more complicated simulation models, and its duration can approach that of the functional simulation with the accuracy remaining acceptable if the workload size is large enough.

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