A high-speed serial interface is the core IP of a high-performance computer, data center and interconnection network; its bandwidth and bit error performance restrict the development of the system. With the evolution of high-speed serial interface line rates from 56 G to 112 G in high-end information systems, their bit errors increase sharply, limiting system performance. In order to solve the high-bit-error problem of the 112 Gb/s high-speed serial interface, this paper proposes a low-error Duo-binary PAM4 (DB-PAM) receive equalization technology. This technology utilizes the Duo-binary (DB) signal in which the channel and the transceiving equalizer work together to realize the low-error reception of the 112 Gb/s signal in the high-attenuation channel. To solve the problem of difficulty in generating high-speed DB-PAM4 signals and the complex adjustment of equalization parameters, this paper proposes a two-step progressive equalization technique. In the first step, the technology transmits not-return-to-zero (NRZ) signals at the transmitter (TX) and generates a Duo-binary (DB) signal path at the receiver using the least mean square error (LMS) algorithm. In the second step, the technology sends a precode-PAM4 (pre-PAM4) signal at TX; at the receiving end, the adaptive equalization algorithm is used to adjust the DSP equalization parameters to generate the optimal equalization parameters of the DB-PAM4 signal. This paper uses Cadence’s AMS simulation platform to verify the receive equalizer of DB-PAM4. Simulation results show: when a 112 Gb/s pre-PAM4 signal passes through the 35 dB@28 GHz channel, the receiver (RX) utilizes the adaptive equalizer to generate a 112 Gb/s DB-PAM4 signal, and the receiver bit error rate (BER) is less than 3e−9.

As the PCIe 6.0 specification places higher requirements on signal integrity and transmission la-tency, it becomes especially important to improve signal transmission performance at the physical layer of the transceiver interface. Retimer circuit as a key component of high-speed serial interface, its delay and jitter size directly affect the overall performance of PCIe. For the conventional Retimer circuit with large latency and low jitter performance, this paper proposes a low latency and low jitter Retimer circuit based on CDR+PLL architecture for PCIe 6.0, using a jitter canceling filter circuit to eliminate the frequency difference between the retiming clock and data, reduce the retiming clock jitter, and improve the quality of Retimer output data; The data is sampled using the retiming clock and then output, avoiding the problem of large penetration latency of con-ventional Retimer circuits. The circuit is designed using CMOS 28nm process. Simulation results show that when 112Gbps PAM4 data is input to the Retimer circuit, the Retimer penetration la-tency is 27.3 ps, which is 83.5% lower than the conventional Retimer structure; the output data jitter is 741 fs, a 31.4% reduction compared to the conventional Retimer structure.

This paper proposes a multichannel and high-bandwidth (BW) receiver for standard packaging die-to-die (D2D) interconnects. The receiver adopts forward clock (FCK) architecture of the high-density transmission standard, which consists of 16 high-speed data paths and a pair of low-speed differential clocks for 512 Gbps BW. To reduce the chip area and power consumption, a common minimal phase-locked loop (MINI-PLL) and data adjustment (CDA) circuit to replaces the clock data recovery circuit (CDR) in the traditional receiver. A delay-matching circuit is adopted to combat PVT variation and lane skew. In addition, a high linearity phase interpolator (PI) circuit design is used in the minimum phase-locked loop (MINI-PLL) to adjust the clock phase and improve the clock jitter performance. Using 28 nm CMOS technology, the overall link power consumption is 1.56 pJ/b. Bit error rate (BER) is less than 10−15 under the real S-parameters with a channel loss of 10db@16GHz.

As the PCIe 6.0 specification places higher requirements on signal integrity and transmission latency, it becomes especially important to improve signal transmission performance at the physical layer of the transceiver interface. Retimer circuits are a key component of high-speed serial interfaces, and their delay and jitter size directly affect the overall performance of PCIe. For the typical retimer circuit with large-latency and low-jitter performance, this paper proposes a low-latency and low-jitter Retimer circuit based on CDR + PLL architecture for PCIe 6.0, using a jitter-canceling filter circuit to eliminate the frequency difference between the retiming clock and data, reduce the retiming clock jitter, and improve the quality of Retimer output data. The data are sampled using the retiming clock and then output, avoiding the problem of large penetration latency of typical retimer circuits. The circuit is designed using the CMOS 28 nm process. Simulation results show that when 112 Gbps PAM4 data are input to the retimer circuit, the Retimer penetration latency is 27.3 ps, which is 83.5% lower than the typical Retimer structure; the output jitter data are 741 fs, a 31.4% reduction compared to the typical retimer structure.

A novel high-speed transceiver based on 7 bit correlated non-return-to-zero(CNRZ-7) with high-bandwidth-density(bandwidth per unit length) and low-power for Die-to-Die(D2D) communication is proposed. In order to further improve the SNR and the bandwidth of the CNRZ-5 in D2D communication, a CNRZ-7 based transmitter matrix and receiver matrix are proposed firstly, which are derived from Walsh Hadamard(W-H) transform and inverse transformation. In addition, to reduce the power consumption of the transmitter, the encoding driver based on CNRZ-7 transmitter matrix is designed with source series terminated drivers(SST). To further improve the SNR of the receiver, the decoding circuit based on CNRZ-7 receiver matrix is designed with a special multi-input comparators(MIC), which contain equalizer circuits. This transceiver is designed with a 28nm CMOS technology and the core area is 0.66mm 2 . The postsimulation results show that this transceiver can operate at 280 Gb/s, and the data rate is 35 Gb/s/wire. The worst width of the receiver's eye-diagrams is 0.45UI when the transceiver operates at a 50 mm PCB channel with a 10dB@20GHz insertion loss, and the total BER is less than 1E-15. The power consumption is 1.1pJ/b under a normal corner.INDEX TERMS Wireline transceiver, correlated non-return-to-zero(CNRZ), Walsh Hadamard, SST, MIC, D2D communication, pin efficiency.