In this paper, we focus on critical issues directly related to the viability of carbon nanotube-based nanoelectromechanical switches, to perform their intended functionality as logic and memory elements, through assessment of typical performance parameters with reference to complementary metal-oxide-semiconductor devices. A detailed analysis of performance metrics regarding threshold voltage control, static and dynamic power dissipation, speed, and integration density is presented. Apart from packaging and reliability issues, these switches seem to be competitive in low power, particularly low-standby power, logic and memory applications.

We compare the level of deterioration in the basic functionality of individual transistors on ASIC chips fabricated in standard 130 nm bulk CMOS technology when subjected to three disparate CVD techniques with relatively low processing temperature to grow carbon nanostructures. We report that the growth technique with the lowest temperature has the least impact on the transistor behavior.