Graphene nanoribbon and transition metal dichalcogenide field-effect transistors (GNRFETs and TMDFETs) have emerged as favorable candidates to replace conventional metal-oxide-semiconductor (MOS) transistor in future technologies. Their competence must be proven through the study and evaluation of various circuits, including static random access memories (SRAMs). Therefore, this paper presents a single-ended 12T (SE12T) SRAM cell designed using GNRFETs and TMDFETs to evaluate their performance. The proposed SE12T cell designed with GNRFETs/TMDFET device improves read static noise margin by 1.95Â/3.20Â and incurs a penalty of 1.16Â/1.14Â in read delay compared to the GNRFETs/TMDFET-based fully differential 8T cell through a read buffer, decoupling the bitline from the storing nodes during the read operation. Furthermore, two transmission gates (TGs) placed inside the cell core cut off the feedback of cross-coupled inverters pair during the write operation, enhancing write static noise margin by 1.65Â/1.71Â. These two TGs along with high logic level of virtual ground (V GND ) control signal during hold mode reduce leakage power. Existence of a higher number of p-type MOS (PMOS) devices, the presence of stacked transistors, and being single-ended bitcell further reduce this metric, nearly 1.48Â/1.17Â designed with GNRFETs/TMDFET device as compared to FD8T. Furthermore, it is observed from the results that GNRFET-based designs have better performance than those of their TMDFET counterparts. The proposed cell eliminates write half-select disturb, and therefore, bit-interleaving architecture can be applied to reduce multi-bit errors.

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