No abstract

This paper presents a quadratic placement algorithm to be applied for 3D circuits. We formulate the 3D problem to control the area balance and the number of 3D-Vias between tiers. We introduce the z-Cell Shifting operation in order to control the area balance. We also define a new operation for the refinement of the solution called 3D Iterative Refinement, that has a control statement to avoid excessive number of 3D-Vias in order to keep the feasibility of our placement solution. After quadratic placement, we move to the placement legalization that is based on min-cost max flow and Simulated Annealing. For detailed placement refinement, we apply Simulated Annealing without cell migration between tiers. Experimental results show that our placement flow targeting one tier is comparable to academic tools such as FastPlace, Capo and Dragon in wire length and running time when targeting a single tier. On multiple tiers, we can reduce the average wire length from 7% (2 tiers) to 32% (5 tiers) and worst wire length by 26% (2 tiers) to 52% (5 tiers). The number of 3D-Vias obtained is feasible since the area overhead introduced is always below 10%.

No abstract

This work introduces a new technique to improve the global placement, which can be applied to any regular placer. We propose an algorithm called Logical Core, based on Google PageRank , which distributes probability weights to every cell in the circuit netlist. Then, these weights are used to select the most important cells for the global placement. By using this information, we are able to improve global placement in terms of wirelength. The Logical Core algorithm proposes a new complexity rule to the placement graph. This complexity has a great similarity with the Rent's Rule. The technique improves the total wirelength in all tested cases by 4.5%.