In this paper, we present different acceleration concepts for the Robust Header Compression version 2 (ROHCv2) algorithms in Long Term Evolution (LTE) handsets. First, we explore the potential performance improvements and energy savings by adopting scratchpad memories at various sizes. Second, dedicated hardware accelerators with different data transfer modes are compared in terms of processing speed and energy efficiency on system level. By applying a virtual prototyping methodology with a proprietary filter module, we are able to investigate these two approaches within a state-of-the-art ARM based mobile phone platform at real software loads. Additionally, combined measurements of the execution time together with an estimation of the energy, that is consumed in the memory and the bus architecture, are performed. With reasonably dimensioned scratchpad memories (16 kB for instructions and data respectively), maximum speedups and energy savings both of approximately 60 % are achieved depending on the cache sizes in the embedded processor. Even better performance, especially in combination with big caches, is reached with a dedicated ROHCv2 hardware accelerator supporting the processing of several packets at once in a so called list mode. Compared to the pure software case, the execution time and the energy consumption are both improved by up to 80 % at small caches and still amount to more than 40 % and almost 30 % at big caches, respectively.

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Even today, safety-critical systems in many fields of application use separate processors to isolate software of different criticality from another. The resulting system architecture is non-optimal in regard to flexibility, device size and power consumption. These drawbacks can be prevented by the use of partitioning operating systems that enable the integration of applications with different criticality on a single processor. However, their application for deeply-embedded devices, that are characterized by strict resource constraints and the lack of advanced processor features such as memorymanagement units (MMU), is challenging. In this work, we show that the impact of virtualization on performance and predictability is smaller in the field of deeply-embedded devices than in more complex systems, making it a compelling choice as a partitioning technology. We present a hypervisor that provides time and space partitioning for an MMU-less system, as well as mechanisms for communication and resource sharing. To satisfy the strict power and resource constraints found in deeply-embedded devices, we focus on solutions with a minimal runtime overhead. Furthermore, the hypervisor is integrated with the processor power management, often enabling significant power savings in the resulting system architecture.