A fully integrated 5-GHz PLL frequency synthesizer for WSN applications has been designed and implemented on TSMC 0.18 µm RF CMOS process. In order to realize low power consumption, VCO adopted 6-bit switch resistors array which could provide varied biasing current by auto current calibration (ACC) circuit. Phase switching technique is also used in the frequency divider to reduce power consumption. In order to realize low phase noise, VCO is designed to have small gain and uses 4-bit switch capacitor array to provide wide tuning range. In order to reduce the locking time of PLL system, fast AFC is proposed. PFD is realized by the typical structure with TSPC dynamic D flip-flop. CP structure applying the replica technology is proposed. With a 1.8V supply voltage, the post-simulated minimum power consumption of the synthesizer is 6.4mW. Finally, the chip size of the frequency synthesizer is 1.11  1.54mm 2 with testing buffer and pads.