By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic (DTCTGAL) circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25 μm CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.

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A bstract-Through the study of the ternary shift register and adiabatic circuit working principle and structure, a new design of ternary adiabatic shift register is proposed in this paper. By using the theory of three essential circuit elements, combining with the adiabatic computing principle, the structure expressions and the corresponding circuit structures of ternary adiabatic flip-flop with the reset port and ternary adiabatic 3 to 1 multiplexer are derived firstly, and then the further design of 4-bit ternary adiabatic shift register is presented. Finally, computer simulations verify the circuits designed have the correct logic function and energy recovery characteristics.

Based on multi-valued logic, adiabatic circuits and the structure of ternary static random access memory (SRAM), a design scheme of a novel ternary clocked adiabatic SRAM is presented. The scheme adopts bootstrapped NMOS transistors, and an address decoder, a storage cell and a sense amplifier are charged and discharged in the adiabatic way, so the charges stored in the large switch capacitance of word lines, bit lines and the address decoder can be effectively restored to achieve energy recovery during reading and writing of ternary signals. The PSPICE simulation results indicate that the ternary clocked adiabatic SRAM has a correct logic function and low power consumption. Compared with ternary conventional SRAM, the average power consumption of the ternary adiabatic SRAM saves up to 68% in the same conditions.

By studying the design principles of multi-valued logic and characteristics of adiabatic circuits, a novel design scheme of ternary adiabatic counter was proposed in this paper. Guided by switch-signal theory, the scheme derives the switch-level structures of ternary adiabatic T -operation circuit, and using bootstrapped NMOS to realize energy input and recovery, then the ternary adiabatic counter is realized by the optimum ternary adiabatic T-operation network which adopting the method of splitting the truth table. Finally, the PSPICE simulation using TSMC O.25f1m CMOS technology validated that the designed circuits have correct logic function and the character of clearly low power.