A power-efficient successive approximation analogue-to-digital converter (SA-ADC) is proposed. In order to reduce the energy consumption of the employed capacitive digital-to-analogue converter (DAC), a new low-energy capacitor switching technique is proposed which consumes no switching energy during the first three comparison steps. Moreover, an energyefficient split-monotonic technique is utilised for the rest of the operations. Compared with the capacitor switching technique used in the conventional SA-ADC, the proposed scheme not only reduces the switching energy by 99.23% but also it has lowered the total capacitor size by 75%. Furthermore, in order to realise the proposed capacitor switching scheme, a powerefficient logic circuit is designed which reduces the power consumption of the required control logic circuit by reducing the activity of the employed D-type flip-flops. Based on the proposed scheme, a 10 bit 40 kS/s SA-ADC has been designed and simulated in a 0.18 µm complementary metal-oxide semiconductor technology with a supply voltage of 1 V. Post-layout simulation results show that the proposed ADC circuit achieves a signal-to-noise-and-distortion ratio of 60.8 dB at the cost of 270 nW power consumption, resulting in a figure-of-merit of 7.6 fJ/conversion step.