Abstract-A bottleneck during hardware design is the localization and the correction of faults -so-called debugging. Several approaches for automation of debugging have been proposed. This paper describes a methodology for evaluation and comparison of automated debugging algorithms. A fault model for faults occurring in SystemC descriptions at design time or during implementation is an essential part of this methodology. Each type of fault is characterized by mutations on the program dependence graph. The presented methodology is applied to evaluate the capability of a simulation based debugging procedure.

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Verification is a major bottleneck in today's circuit and system design. This includes the tasks of error detection, error localization, and error correction in an implemented design as well as the analysis and avoidance of transient faults. For all those tasks, knowing for how long values of signals influence the system is important.In this paper, we propose a minimal and maximal latency measure for sequential circuits. This measure explains how long a circuit's state and outputs depend on input stimuli. Exact and heuristic algorithms are proposed to determine the measure. Experiments show that the measure provides insight into the behavior of circuit designs.