This paper describes a Deep Brain Stimulation device, portable, for chronic experiments on rodents in the context of Parkinson's disease. Our goal is to equip the animal with a device that mimics the human therapeutic conditions. It implies to respect a set of properties such as bilateral current-mode and charge-balanced stimulation, as well as programmability, low power consumption and re-usability to finally reach a suitable weight for long-term experiments. After the analysis of the solutions found in the literature, the full design of the device is explained. First, the stimulation front-end circuit driven by a processor unit, then the choice of supply sources which is a critical point for the weight and life-time of our system. Our low cost system has been realized using commercial discrete components and the overall power consumption was minimized. We achieved 6 days of maximal current stimulation with the chosen battery for a weight of 13.8 g . Finally, the device was carried out in vivo on rats during a 3 weeks experiment as the used implantation technique allows battery changing. This experiment also permits to emphasize the mechanical aspects including the packaging and electrodes holding.

Abstract-To deal with Wireless Sensor Node's energy constraints, new architectural solutions have to be found. This paper proposes to analyze a WSN microcontroller sub-system power consumption to extract the main power contributors according to different applicative execution phases. The objective is to come out with the energy reduction potentiality offered by an additional module called Wake-Up Controller. This block is able to substitute to the main CPU for current tasks like data transfers between sensors, memories or radio and fine grain power/frequency management of the entire node's sub-modules. Power simulations of a microcontroller sub-system based on FDSOI28 technology, with and without the Wake-Up Controller use, are proposed. Results are presented for applicative scenarios ranging from very low to high activity rates. This study exhibits power gains from 14.5% to 76% in the full range attesting the future design of this new module.

Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning on components as the application needs it. As wake up sources may be diverse, simple controllers are integrated to handle smart wake up schemes. Therefore, to prevent overconsumption while transitioning to running mode, fast wake up sequences are required. An asynchronous 16-bit Reduced Instruction Set Computer (RISC) Wake-up Controller (WuC) is proposed demonstrating 50.5 ns@9.2 Million Instructions Per Second (MIPS)@0.6 V wake-up latency, drastically reducing the overall wake-up energy of IoT systems. A clockless implementation of the controller saves the booting time and the power consumption of a clock generator, while providing high robustness to environmental variations such as supply voltage level. The WuC is also able to run simple tasks with a reduced Instruction Set Architecture (ISA) and achieves as low as 11.2 pJ/inst @0.5 V in Fully Depleted Silicon On Insulator (FDSOI) 28 nm.