Single-ISA heterogeneous multicore processors have gained increasing popularity with the introduction of recent technologies such as ARM big.LITTLE. These processors offer increased energy efficiency through combining low power inorder cores with high performance out-of-order cores. Efficiently exploiting this attractive feature requires careful management so as to meet the demands of targeted applications. In this paper, we explore the design of those architectures based on the ARM big.LITTLE technology by modeling performance and power in gem5 and McPAT frameworks. Our models are validated w.r.t. the Samsung Exynos 5 Octa (5422) chip. We show average errors of 20% in execution time, 13% for power consumption and 24% for energy-to-solution.

International audienceAs complexity of embedded system increases, configurable hardware is becoming more attractive because it provides a fast and efficient basis for design development. As a consequence, one of the most promising embedded architecture consists in the replication of Processing Elements (PEs)connected through a Network-on-Chip (NoC). Such architectures provide computation parallelism, scalability, and reduced design time thanks to reusability. This paper describes the development of a scalable, distributed memory, open-source NoC-based platform called Open-Scale and itsimplementation into FPGA devices. The main objective of this platform is to provide a complete framework for research development on NoC-based distributed memory MPSoCs

Lightweight cryptography has recently emerged as a strong requirement for any highly constrained connected device; encryption/decryption processes must strike the balance between speed, area, power efficiency, and security robustness. The aim of this paper is to study the potential gains of the lightweight cryptography algorithms compared to the classic ones in hardware implementation. Advanced Encryption Standard (AES) as the standard, PRESENT and the very recently published GIFT are considered along with several optimized hardware versions of each one. Low-and high-security levels with 80-and 128bit key length respectively are compared. They are all implemented on a Xilinx Kintex-7 FPGA, exploiting different slice configurations to evaluate their performances. The results show the expected benefits in terms of throughput and area, which allows selecting the best lightweight crypto-ciphers depending on the target device or application. In addition, correlation power analysis is performed on each cipher to estimate their resistance against side-channel analysis. INDEX TERMS Lightweight cryptography, block cipher, substitution-permutation-network, advanced encryption standard (AES), PRESENT, GIFT.