This paper presents a simple method for standard cell optimization in the subthreshold regime. Through proper dimensioning of the transistor length and width an improved symmetric propagation delay and a reduction in dynamic power consumption compared to conventional CMOS standard cell implementations is achieved. The performance of the presented cells has been verified using logic gate arrays and ring oscillators with high number of stages. The measurement results reasonably agree with simulation data.
This work presents the implementation of an asynchronous event detector circuit by applying subthreshold standard cells. The presented circuit operates in an on-chip power management unit (PMU) of a wireless sensor node. Such an application demands an ultra-low power architecture for an increased overall lifetime of the sensor node. The asynchronous circuit architecture and its subthreshold logic implementation both significantly reduce the leakage power dissipation by factor three. The presented event detector is realized in a 130 nm CMOS process with regular transistors operating from a 200 mV supply voltage.
This paper presents an overview of wireless integrated sensor node realizations for indoor monitoring and localization applications. Depending on the targeted application scenario different wireless sensor node implementations based on either high-performance processors or semi-passive radio-frequency identification (RFID) cores are outlined. The presented high-performance node realization with monitoring and seamless indoor and outdoor localization capability can operate independently for a duration of one day and additionally features wireless charging. Furthermore, a UHF RFID Gen2 sensor tag for indoor localization and fall detection is presented that enables a battery lifetime of approximately one month. Finally, ultra-low-power UHF RFID sensor node concepts based on sub-threshold wake-up receivers are introduced that can achieve operational times of several years for specific low duty cycle scenarios.
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